In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.

Rapid advances in integrated circuit technology based on binary logic have made possible the fabrication of digital circuits or digital VLSI systems with not only a very large number of devices on a single chip or wafer, but also high-speed processing capability. However, the advance of processing speeds and improvement in cost/performance ratio based on conventional binary logic will not always continue unabated in submicron geometry. Submicron integrated circuits can handle multiple-valued signals at high speed rather than binary signals, especially at data communication level because of the reduced interconnections. The use of nonbinary logic or discrete-analog signal processing will not be out of the question if the multiple-valued hardware algorithms are developed for fast parallel operations. Moreover, in VLSI or ULSI processors the delay time due to global communications between functional modules or chips instead of each functional module itself is the most important factors to determine the total performance. Locally computable hardware implementation and new parallel hardware algorithms natural to multiple-valued data representation and circuit technologies are the key properties to develop VLSI processors in submicron geometry. As a result, multiple-valued VLSI processors make it possible to improve the effective chip density together with the processing speed significantly. In this paper, we summarize several potential advantages of multiple-valued VLSI processors in submicron geometry due to great reduction of interconnection and due to the suitability to locally computable hardware implementation, and demonstrate that some examples of special-purpose multiple-valued VLSI processors, which are a signed-digit arithmetic VLSI processor, a residue arithmetic VLSI processor and a matching VLSI processor can achieve higher performance for real-world computing system.

Although the perception of gloss is based on human visual perception, some methods for measuring glossiness, in contrast to human ability, have been proposed involving plane surfaces. Glossiness defined in these methods, however, does not correspond with psychological glossiness perceived by the human eye over the wide range from relatively low gloss to high gloss. In addition, the change in the incident angle causes a deviation in the measurement of glossiness. A new method for measuring glossiness is proposed in this study. For the new definition of glossiness Gd, the brightness function is utilized. We also extract the value of smoothness of the object's surfaces for use as a factor of glossiness. The measuring equipment consists of a light source, an optical system and a personal computer. Glossiness Gd of paper and plastics is measured with the use of this equipment. In all samples, a strong correlation, with a correlation coefficient of more than 0.97, has been observed between Gd and psychological glossiness Gph. The variance of measured glossiness due to the change in the incident angle of light is small in comparison with that of conventional methods. Based on these findings, it has been found that this method is useful for measuring glossiness of plane objects in the range from relatively low gloss to high gloss.

An adder-based arithmetic VLSI processor using the SD number system is proposed for the applications of real-time computation such as intelligent robot system. Especially in the intelligent robot control system, not only high throughput but also small latency is a very important subject to make quick response for the sensor feedback situation, because the next input sample is obtained only after the robot actually moves. It is essential in the VLSI architecture for the intelligent robot system to make the latency as small as possible. The use of parallelism is an effective approach to reduce the latency. To meet the requirement, an architecture of a new multiple-valued arithmetic VLSI processor is developed. In the processor, addition and subtraction are performed by using the single adderbased processing element (PE). More complex basic arithmetic operations such as multiplication and division are performed by the appropriate data communications between the adder-based PEs with preserving their parallelism. In the proposed architecture, fine-grain parallel processing at the adder-based PE level is realized, and all the PEs can be fully utilized for any parallel arithmetic operations according to adder-based data dependency graph. As a result, the processing speed will be greatly increased in comparison with the conventional parallel processors having the different kinds of the arithmetic PEs such as an adder, a multiplier and a divider. To realize the arithmetic VLSI processor using the adder-based PEs, we introduce the signed-digit (SD) number system for the parallel arithmetic operations because the SD arithmetic has the advantage of modularity as well as parallelism. The multiple-valued bidirectional currentmode technology is also used for the implementation of the compact and high-speed adder-based PE, and the reduction of the number of the interconnections. It is demonstrated that these advantges of the multiple-valued technology are fully used for the implementation of the arithmetic VLSI processor. As a result, the latency of the proposed multiple-valued processor is reduced to 25% that of the binary processor integrated in the same chip size.

Low-sensitivity digital filters are required for accurate signal processing. Among many low-sensitivity digital filters, a method using complex allpass circuits is well-known. In this paper, a new synthesis of complex allpass circuits is proposed. The proposed synthesis can be realized more easily either only in the z-domain or in the s-domain than conventional methods. The key concept for the synthesis is based on the factorization of lossless scattering matrices. Complex allpass circuits are interpreted as lossless digital two-port circuits, whose scattering matrices are factored. Furthermore, in the cases of Butterworth, Chebyshev and inverse Chebyshev responses, the explicit formulae for multiplier coefficients are derived, which enable us to synthesize the objective circuits directly from the specifications in the s-domain. Finally design examples verify the effectiveness of the proposed method.

The demand for high-speed image processing is obvious in many real-world computations such as robot vision. Not only high throughput but also small latency becomes an important factor of the performance, because of the requirement of frequent visual feedback. In this paper, a high-performance VLSI image processor based on the multiple-valued residue arithmetic circuit is proposed for such applications. Parallelism is hierarchically used to realize the high-performance VLSI image processor. First, spatially parallel architecture that is different from pipeline architecture is considered to reduce the latency. Secondly, residue number arithmetic is introduced. In the residue number arithmetic, data communication between the mod mi arithmetic units is not necessary, so that multiple mod mi arithmetic units can be completely separated to different chips. Therefore, a number of mod mi multiply adders can be implemented on a single VLSI chip based on the modulus-slice concept. Finally, each mod mi arithmetic unit can be effectively implemented in parallel structure using the concept of a pseudoprimitive root and the multiple-valued current-mode circuit technology. Thus, it is made clear that the throughout use of parallelism makes the latency 1/3 in comparison with the ordinary binary implementation.

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.

This article analyzes the property of the fully interconnected neural networks as a method of solving combinatorial optimization problems in general. In particular, in order to escape local minimums in this model, we analyze theoretically the relation between the diagonal elements of the connection matrix and the stability of the networks. It is shown that the position of the global minimum point of the energy function on the hyper sphere in n dimensional space is given by the eigen vector corresponding the maximum eigen value of the connection matrix. Then it is shown that the diagonal elements of the connection matrix can be improved without loss of generality. The equilibrium points of the improved networks are classified according to their properties, and their stability is investigated. In order to show that the change of the diagonal elements improves the potential for the global minimum search, computer simulations are carried out by using the theoretical values. In according to the simulation result on 10 neurons, the success rate to get the optimum solution is 97.5%. The result shows that the improvement of the diagonal elements has potential for minimum search.

In this paper, two models for associative memory based on a measure of manhattan length are proposed. First, we propose the two-layered model which has an advantage to its implementation by using PDN. We also refer to the way to improve the recalling ability of this model against noisy input patterns. Secondly, we propose the other model which always recalls the nearest memory pattern in a measure of manhattan length by lateral inhibition. Even if a noise of input pattern is so large that the first model can not recall, this model can recall correctly against such a noisy pattern. We also confirm the performance of the two models by computer simulations.

A new class of the universal representation for the positive integers is proposed. The positive integers are divided into infinite groups, and each positive integer n is represented by a pair of integers (p,q), which means that n is the q-th number in the p-th group. It is shown that the new class includes the message length strategy as a special case, and the asymptotically optimal representation can easily be realized. Furthermore, a new asymptotically and practically efficient representation scheme is proposed, which preserves the numerical, lexicographical, and length orders.

This paper describes a mixed mode circuit simulation by the direct and relaxation-based methods with dynamic network partitioning. For the efficient circuit simulation by the direct method, the algorithms with circuit partitioning and latency technique have been studied. Recently, the hierarchical decomposition and latency and their validities have been researched. Network tearing techniques enable independent analysis of each subnetwork except for the local datum nodes. Therefore, if the local datum nodes are also torn, each subnetwork is separated entirely. Since the network separation is based on relaxation approach, the implementation of the separation technique in the circuit simulation by the direct method corresponds to performing the mixed mode simulation by the direct and relaxation-based methods. In this paper, a dynamic "network separation" technique based on the tightness of the coupling between subnetworks is suggested. Then, by the introduction of dynamic network separation into the simulator SPLIT with hierarchical decomposition and latency, the mixed mode circuit simulator, which selects the direct method or the relaxation method and determines the block size of the latent circuit dynamically and suitably, is constructed.

This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1Gbit/s.

In conventional trellis coded modulation (TCM), a bit rate of m/m+1 convolutional encoder is employed for n information bits (mn), where 2n+1 signal points are required. In this paper, we propose a novel TCM system using totally overlapped signal sets (TO-TCM), i.e., each signal point is used twice. Thus, TO-TCM can realize only half signal points (2n) comparing with those of a conventional TCM system (2n+1), and it is possible to implement a coded modulation system without doubling the signal points by an insertion of redundant bits. The cases of the proposed schemes which have a process to extend the minimum free distances between the signal points can achieve a considerable coding gain in comparison to the traditional uncoded systems with 2n signal points. Moreover, as the proposed scheme needs only half signal points (2n) of those of conventional TCM, the average power is lower and it is less sensitive to the carrier phase offset.

Asynchronous Transfer Mode (ATM) is an information transport technique that well supports Broadband ISDN (B-ISDN). One unsolved problem to the perfection of ATM networks is to provide a testing environment that conforms to some standardized network management scheme. From this point of view, remotely controlled virtual path testing is considered in this paper. Remotely controlled virtual path testing should be executed through the standardized Telecommunications Management Network (TMN) model, which employs the OSI systems management concept as the basis of information exchange. Thus, this paper addresses the two issues that arise when OSI systems management standards are applied to virtual path testing. One issue is to define relevant information models. The other issue is to provide test resources with a concurrency control mechanism that guarantees a consistent test environment without causing deadlocks. To resolve these issues, technical requirements are clarified for the remote control of test resources. Next, alternatives to the concurrency control mechanism are shown and compared through computer simulations. A method of defining information models is then proposed. The proposed method ensures the easy storage and retrieval of intermediate test results as well as permitting the effective provision of concurrency control for test resources. An application scenario is also derived. The scenario shows that tests can be executed by using standardized communication services. These results confirm that virtual path testing can be successfully achieved in conformance with the OSI systems management standards.

In this paper, a design method is described for very low sensitivity fully-balanced narrow-band band-pass switched-capacitor filters (SCF's) whose worst-case sensitivities of the amplitude responses become zero at every reflection zero. The proposed method is based on applying the low-pass to high-pass transformation, the pseudo two-path technique and the capacitance-ratio reduction technique to very low sensitivity low-pass SC ladder filters. A design example of the band-pass SCF with a quality factor Q250 is given to verify the proposed method. The remarkable advantages of this approach are very low sensitivity to element-value variations, a small capacitance spread, a small total capacitance, and clock-feedthrough noise immunity inside the passband.

In a coherent optical communication system, a polarization fluctuation of an optical fiber is one of the most important problem. On the other hand, for a realization of optical devices, dielectric waveguides with sinusoidally varying width are investigated. Knowledge of the electromagnetic field distribution in a dielectric waveguide with boundary perturbed time by time becomes a very interesting problem. This paper shows a numerical method to simulate the effect of the external disturbance against the dielectric waveguide from time to time. The author has discussed body fitted grid generation with moving boundary for the Poisson's equation and the Laplace's equation. Here we apply this theory for the dielectric waveguide. The technique employs a kind of an expanded numerical grid generation. As the author added time component to grid generation, the time dependent coordinate system which coincides with a contour of moving boundary could be transformed into fixed rectangular coordinate system. Two cases of the perturbations against the dielectric waveguide are treated. In the first case, we present the electric distribution in the dielectric waveguide perturbed along a propagation path. While in the second case, the electric field in the waveguide perturbed perpendicular to the propagation path. Such phenomena that the phase of the electric field modulated by the external perturbation are clarified by numerical results. This technique makes it possible not only to analyze the effect of the external disturbance in a coherent optical communication system but also to fabricate optical modulators or couplers.

We propose a direct-sequence spread-spectrum multi-access (DS/SSMA) receiver that incorporates multipath diversity combining and multistage co-channel interference (CCI) cancellation. This receiver structure which is more resistant to the near/far problem essentially removes more and more of the CCI with each successive cancellation stage. With the assumption that perfect channel estimates have been obtained, we analyze the bit error rate (BER) performance of this system when received powers are unequal. Results show that the BER can approach that of a single-user case as the number of CCI cancellation stages increases.

In this paper, some misconceptions about "multipath propagation" are discussed for those propagation engineers, who are not familiar with the close relationship between multipath propagation and a communication system in a mobile/portable radio communication environment. It is shown that believed facts about multipath propagation are not always true. Namely, it is well-known that multipath propagation is undesirable if a conventional sample-and-decision receiver is assumed. It is not well-recognized that it can be a desirable phenomenon if a sophisticated communication system uses adaptive equalization, anti-multipath modulation, or spread spectrum communication, for example. On the other hand, it is widely accepted that root mean square (rms) multipath delay spread is a good measure of bit-error-rate performance, i.e., as rms delay spread gets larger, bit-error-rate generally gets worse. However, it is pointed out that this is not always true, especially in propagation conditions with very long-delayed multipath signals. In short, it is the purpose of this paper to show examples that the facts believed to be true sometimes turn out to be false, unless we pay attention to both aspects of propagation and system design in the field of mobile/portable radio communications. In fact, for highly efficient communication systems design, propagation, antenna and system factors should be taken into account simultaneously.

In this paper, we study the performance of convolutional coding using an error-and-erasure correction Viterbi decoder for π/4-shift QDPSK mobile radio transmission. The receiver uses received signal envelope as channel state information to erase unreliable symbols instead of making explicit decision before decoding. The performance study is carried out over frequency-selective fading channel with additive white Gaussian noise, co-channel interference and propagation delay spread. The results show that decoding with symbol erasure can significantly improve the system transmission performance compared to decoding without symbol erasure.

Research in optical microwave interaction, at its earlier stages, was spured by the desire to make an optically fed and controlled phased array antenna with monolithic microwave integrated circuit (MMIC) transmit/receive (T/R) modules. In the first part of this paper experimental results are presented demonstrating an optically fed phased array antenna operating at C-band in the 5.5 to 5.8 GHz frequency range. The present system consists of two optically fed 14 subarrays with MMIC based active T/R modules. Custom designed fiber optic links have been employed to provide distribution of data and frequency reference signals to phased array antenna. One of the challenges of the future is the development of better interfaces between electronic (microwave) and optical components, including the chip level merging of photonic and electronic components on III-V compounds. This aspect of the research is covered in the second half of the paper.