Video service is slated to be a major application of emerging high-speed communications networks of the future. In particular, full-motion video is designed to take advantage of the high bandwidths that will become affordably available with the advent of B-ISDN. A salient feature of compressed video sources is that they give rise to autocorrelated traffic streams, which are difficult to model with traditional modeling techniques. In this paper, we describe a new methodology, called TES (Transform-Expand-Sample) , for modeling general autocorrelated time series, and we apply it to traffic modeling of compressed video. The main characteristic of this methodology is that it can model an arbitrary marginal distribution and approximate the autocorrelation structure of an empirical sample such as traffic measurements. Furthermore, the empirical marginal (histogram) and leading autocorrelations are captured simultaneously. Practical TES modeling is computationally intensive and is effectively carried out with software support. A computerized modeling environment, called TEStool, is briefly reviewed. TEStool supports a heuristic search approach for fitting a TES model to empirical time series. Finally, we exemplify our approach by two examples of TES video source models, constructed from empirical codec bitrate measurements: one at the frame level and the other at the group-of-block level. The examples demonstrate the efficacy of the TES modeling methodology and the TEStool modeling environment.

A detailed numerical solution of the design criteria of in-phase lateral and single-longitudinal-mode operation GaInAsP/InP DFB laser arrays is presented. The analysis, including broad-area pumped and stripe-geometry pumped index-guided arrays, was carried out on the basis of the eigenvalue equation method. It is shown that there exists a cut-off array pitch co, at which all of the higher-order array modes are cut off. For the pitch larger than the cut-off pitch co, the modal discrimination is evaluated by the threshold gain difference between the in-phase lateral and higher-order array modes. As a result, the modal discrimination was found to decrease with the increase of the number of elements and the array pitch which is limited to be smaller than twice the cut-off pitch co to attain a stable in-phase lateral- and single-longitudinal-mode operation.

Frequency Selective Screens (FSS) with conductor or complementary aperture array are investigated. The electric current distribution on conductor or the magnetic current distribution on aperture is determined by the moment method in the spectral domain. In addition, the power reflection coefficients are calculated and the scattering properties are considered.

In this paper, we propose a new network organizing method for packet radio networks, a layered self-organizing method. In the layered self-organizing network, whole service area is divided into multiple sub-areas and one base station is settled in each sub-area. Communication links are settled in shorter time than the conventional self-organizing method. We evaluate the network organizing performance of the method by using simulations.

Chaotic behavior in a series resonance circuit with a ferroelectric triglycine sulfate (TGS) crystal was observed just below the ferroelectric phase transition temperature. We have analyzed the nonlinear responses by applying external electric fields to the crystal. The computer simulation was made for the modified forroelectric hysteresis loops to realize the experimental results. The fractal correlation dimension was determined to be ν=1.8 in the chaotic phase.

We analyzed vergence change by moving both the target and the subject toward depth direction simultaneously. It has been suggested that the command for vergence movement caused by depth-direction-head-movement and that caused by target movement are generated separately, then combined in the oculomotor system.

Hot carrier stressing is carried out on ultra-thin-film SOI/pMOSFET's under a front gate operation. Degradations of both front and back gate characteristics are estimated. Effects of trapped electron in the front and the back gate oxide on device characteristics are also estimated. In a triode region, it is found that degradation in front gate characteristics is correlated with that in back gate characteristics, although ΔVth(b) is twenty times as large as ΔVth(f), due to difference between the front gate and the buried oxide thickness. In a pentode region, Δβ/β0 in a forward-mode is larger than that in a reverse-mode. This is because of the non-uniformly distributed hot carrier damage along the channel. Based on the charge-coupling theory, damages in the front gate and buried oxide by hot carrier effects are estimated separately. Flat-band-voltage shift in the back gate due to trapped charges in the buried oxide, is obtained from Vth (f) dependence on back gate bias. For Leff=2.0 µm devices, the flat-band-voltage shift varies in the range of 1.00 to 1.50 V. This indicates that trapped electrons are created in the buried oxide. Trapped electrons in the buried oxide increase gm(f) through the effect equivalent to back gate bias. From gm(f) dependence on back gate bias, it is found that effective channel length is decreased by trapped electrons in the front gate oxide near the drain. Therefore, it is worth noticing that, in hot carrier effects in ultra-thin-film SOI/pMOSFET's, gm is increased not only by the reduction of effective channel length but also by the equivalent back gate bias effect.

A 0.1-µm-gate CMOS/SIMOX has been successfully fabricated using high quality SIMOX substrates. The propagation delay time for the 0.1-µm-gate CMOS/SIMOX is not so noticeable due to the parasitic resistance of the source and drain regions. We anticipate 0.1-µm-gate CMOS/SIMOX devices with a delay time of less than 20 ps at a supply voltage of 1.5 V by reducing the remaining parasitic resistance and capacitances.

We fabricated a 4 GHz thin-base (120 nm) lateral bipolar transistor on bonded SOI by applying our sidewall self-aligning base process. By applying this device to BiCMOS circuits, bipolar transistor base junction capacitance, and MOSFET source and drain capacitance were very small. Furthermore, MOSFET and bipolar transistors are completely isolated from each other. Thus, it is easy to optimize MOS and bipolar processes, and provide protection from latch-up problems and soft errors caused by α-particles. In this paper, we describe device characteristics and discuss the crystal quality degradation introduced by ion implantation, and two dimensional effects of base diffusion capacitance.

The design of N-dimensional (N-D) FIR filters requires in general an enormous computational effort. One of the most successful methods for design and implementation is the McClellan transformation. In this paper a numerically simple technique for determining the coefficients of the transformation is suggested. This appears to be the simplest available method for the design of N-D hyperspherically symmetric FIR filters with excellent symmetry.

Synchronous clocks are an essential requirement for a variety of distributed system applications. Many of these applications are safety-critical and require fault tolerance. In this paper, a general probabilistic clock synchronization model is presented. This model is uniformly probabilistic, incorporating random message delays, random clock drifts, and random fault occurrences. The model allows faults in any system component and of any type. Also, a new Sliding Window Clock Synchronization Algorithm (SWA) providing increased fault tolerance is proposed. The probabilistic model is used for an evaluation of SWA which shows that SWA is capable of tolerating significantly more faults than other algorithms and that the synchronization tightness is as good or better than that of other algorithms.

If a perspective of the "256M/1G era" were to be made from this present, namely the last stage of the development of 64 M DRAMs, the process technologies will show a variety of progress. Some of them would remain only in the extension of the present ones, but others would show a fundamental change including their technological constitutions. The optical lithography will survive even the "256M/1G era" mainly with the innovations of mask technologies. The etching technologies will remain basically the same as the present ones, but will be much more refined. The studies on plasma/redical related surface reactions, however, will bring a variety of surface treatment technologies of new function. The interconnection technologies will encounter various kinds of difficulties both in materials and in processign, and mechanical processing will become one of ULSI processing technologies. The shallow junction technology will merge with the metallization and epitaxial growth technology. The thin dielectrics will approach a critical situation, and it might enhance the device structural change to three dimensional ones. Corresponding to this, the necessity of "vertical processing" will become larger. The bonding SOI technology might overcome these situations of increasing difficulties. On the other hand, the contamination control will be the base of these technology innovations and improvements, exploring a new technology field in addition to the conventional process technology fields.

The characteristics of voltage-resonant dc-dc converters have already been analyzed and described. However, in the conventional analysis, the inductance of the reactor is assumed to be infinity and the loss resistance of the power circuit is not taken into account. Also, in some cases, the averaging method is applied to analyze the resonant dc-dc converters as well as the pwm dc-dc converters. Consequently, the results from conventional analysis are not entirely in agreement with the experimental ones. This paper presents a general design-oriented analysis of the buck-boost type voltage-resonant dc-dc converter in the continuous and discontinuous modes of the reactor current. In this analysis, the loss resistance in each part of the power circuit, the inductance of the reactor, the effective value (not mean value) of the power loss, and the energy-balance among the input, output and internal-loss powers are taken into account. As a result, the behavior and characteristics of the buck-boost type voltage-resonant dc-dc converter are fully explained. It is also revealed that there is a useful mode in the discontinuous reactor current region, in which the output voltage can be regulated sufficiently for the load change from no load to full load and for the relatively large change of the input voltage, and then the change in the switching frequency can be kept relatively small.

A 0.4 µm stacked gate cell for a 64 Mbit flash memory has been developed which has the Symmetrical Side Wall Diffusion Self Aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p+ pockets at both the drain and the source, and adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the channel erasing scheme applying negative bias to the gate, which is adopted for the SSW-DSA cell, shows lower trapped charges after Write/Erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance an retention characteristics than conventional erasing schemes.

The pressure waveforms indicated on a catheter manometer system are subject to serious distortion due to the resonance of the catheter itself, or the compliance of a particular transducer. Although several methods have been proposed for improving those characteristics, they ahave never been put into practice. We have focused on the transfer function of the catheter manometer, and made a pilot system, using the natural observation method. This method has been suggested as a means of studying the structure of the instantaneous waveform. In this manner, we were able to increace the bandwidth in the ferquency domain and reduce the ringing in the time domain. Correction was performed automatically, using a step wave. Reproduction of the waveform with a flushing device, was a task of equal simplicity, that allowed us to estimate the system parameters so that the response waveform became step-like. In the experiment, our system provided distortion-free left-ventricular pressure waveform measurements and exact evaluation of the cardiac pumping system. The values obtained came much closer to the original figures arrived at by the catheter-tip manometer system.

An acoustic echo canceller that also cancels room noise is proposed. This system has an additive (noise reference) input port, and a noise canceller (NC) precedes the echo canceller (EC) in a cascade configuration. The adaptation control problem for the cascaded echo and noise canceller is solved by controlling the adaptation process to match the occurrence of intermittent speech/echo; the room noise is a stationary signal. A simulation shows that adaptation using the NLMS algorithm is very effective for the echo and noise cancellation. Sub-band cancelling techniques are utilized. Noise cancellation is realized with a lower band EC. Hardware is implemented and its performance evaluated through experiments under a real acoustic field. The combination of the EC with NC maintains excellent performance at all echo to room noise power ratios. It is shown that the proposed canceller overcomes the disadvantages traditionally associated with ECs and NSc.

A newly developed planar inductor and its application to dc-dc converters are described. The planar inductor consists of a planar spiral coil and soft magnetic sheets, it has a small size (11110.8mm), 33µH inductance and a maximum quality factor of 14. The step down chopper dc-dc converter has been developed by using planar inductor, which has small size (20154mm), 5V-2W typical output and output power/volume ratio of 1.7W/cc. The switching converter can be miniaturized by using the planar inductor.

Existing solid models often contain redundant primitives and null blocks, which both slows down the rendering process and makes the process complex. There has been recent progress toward solving this problem, but existing modeling schemes cannot support eliminating all the redundancies, especially the null blocks, from the solid models. This paper proposed a technique that can eliminate redundancies. By dividing a primitive into some surface dispersed points, a new primitive representation is obtained. The sample segments of the primitive or the object are used to locate composition position to prevent the null primitives from being generated. By drawing out the geometric shape points set corresponding to a common acting area, the volume boundary of a primitive or an object is evaluated by only the Boolean set operations. The null blocks can be picked out in terms of the volume boundary. The resulting solid model generated in this way has no redundancies and is suitable for fast rendering of the image.

A new circuit and a transformer structure is described for a high-input-voltage converter operating at a high switching frequency. The two-MOSFET forward converter is suitable for a high-input-voltage converter. To increase the switching frequency, the reset period of the transformer core flux must be reduced. There are a few methods for decreasing the reset period. Increasing the transformer flyback voltage and reducing its stray capacitance are effective in decreasing the reset period without increasing power loss. A new two-MOSFET forward converter is proposed which uset the increased flyback voltage and a transformer structure to reduce the stray capacitance. The new converter using this transformer provides the basis for a 48-V, 100-W output, 270-V input converter operating at 200kHz with high efficiency (above 95%).

Signature analysis using a Multiple-Input LFSR as the output response compaction circuit is widely adopted in actual BIST schemes. While aliasing probabilities for random errors are usually very small, MI-LFSRs are tend to fail detecting diagonal errors. A spot error, which include the diagonal error as a particular case, is defined as multiple bit crrors adjacent in space and in time domain. Then, shuffling of interconnection between CUT output and MI-LFSR input is studied as a scheme to prevent aliasing for such errors. The condition for preventing aliasing due to a predetermined size of single spot error is shown. Block based shuffling and the shortened one are proposed to realize required distance properties. Effect of shuffling for multiple spot errors is examined by simulation showing that shuffling is effective also for a certain extend of multiple spot errors.