In this paper, we develop a novel method for tuning parameters known as the sensitivity parameters of membership functions used in a fuzzy classifier. The proposed method performs tuning by solving a set of inequalities. Each inequality represents a range of the ratio of the sensitivity parameters between the corresponding pair of classes. The range ensures the maximum classification rate for data of the two corresponding classes used for tuning. First, we discuss how such a set of inequalities is derived. We then propose an algorithm to solve the derived set of inequalities. We demonstrate the effectiveness of the proposed tuning method using two classification problems, namely, classification of commonly used iris data, and recognition of vehicle licence plates. The results are compared with those obtained by using the existing tuning method and with those by neural networks.

Optimization of InGaAs/InAlAs multiple quantum well structures for high-speed and low-driving modulation, as well as polarization insensitivity and low chirp, was investigated as a function of well thickness and strain magnitude. As a result, very short optical pulses with 4-6 ps was obtained using a low driving-voltage (<2. 0 Vpp) electroabsorption modulator module operating at a 40-GHz large signal modulation. Small chirp operation for low insertion loss (<8 dB from fiber-to-fiber) with prebias was also demonstrated and the product of the pulse width and the spectral width was estimated to be 0. 39 for a 5 ps pulse width that is nearly transform-limited.

This paper presents a new scheme to estimate depth in a natural three-dimensional scene using a multi-viewpoint image set. In the conventional Multiple-Baseline Stereo (MBS) scheme for the image set, although errors of stereo matching are somewhat reduced by using multiple stereo pairs, the use of square blocks of fixed size sometimes causes false matching, especially, in that image area where occlusion occurs and that image area of small variance of brightness levels. In the proposed scheme, the reference image is segmented into regions which are capable of being arbitrarily shaped, and a depth value is estimated for each region. Also, by comparing the image generated by projection with the original image, depth values are newly estimated in a top-down manner. Then, the error of the previous depth value is detected, and it is corrected. The results of experiments show advantages of the proposed scheme over the MBS scheme.

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (1. 5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 µW, it has a sufficient input range, whereas conventional Wang's OTA needs 703 µW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.

In this paper, we describe the properties of an external cavity modelocked semiconductor laser with a tunability of wavelength, pulse width and repetition rate. This modelocked laser generates optical pulses with pulse widths down to 180 fs and with repetition rates up to 14 GHz in a 120 nm wavelength range near 1. 55 µm or 1. 3 µm. The generated pulses are close to the transform limit and are therefore suitable for very high speed communication systems. In addition to the tunability, this pulse source is a compact and mechanically stable device. We report on two applications of this pulse source in optical time division multiplexing experiments. In the first example the modelocked laser is used as an all-optical clock recovery. In the second example the modelocked laser was used to characterize an interferometric switch by pump-probe experiments.

When a set of objects is shared among several applications, multiple implementations for the set are required in order to suit each application as much as possible. Furthermore, if a set of objects could have multiple implementations, the following issues arise: (1) how to select the best implementation when processing queries on the set, and (2) how to propagate updates on an implementation of the set to the others. In this paper we propose a mechanism of multiple implementations for a set, and also give a solution for the latter issue. In the proposal a set can be of multiple types, and each of the types corresponds to an implementation already contained within the set. Update propagation can be achieved by a rewriting technique at compilation time. We also present a performance study in which the feasibility and effectiveness of our proposal were examined.

We consider statistical multiplexing for various types of input data with different statistics in an integrated multimedia system such as ATM networks. The system is assumed to have a constant service rate and a finite buffer. The bit-rate of each data input is variable and is modeled by a fractional Brownian motion process. Under a criterion of quality of service, we obtain an acceptable region of statistical multiplexing. We introduce a new method of investigating the acceptable region of a statistical multiplexer. The results show that transmitting multitype input processes will increase the multiplexing gain.

A 2-GHz monolithic Si-bipolar logarithmic/ limiting amplifier is described. It features a waveform-dependent current phase shifter that compensates for the intrinsic dependence of unit-amplifier phase shifts on input signal amplitudes and layout techniques that minimize crosstalk in Si substrate. The amplifier dissipates 250 mW at a 3-V supply, which is less than 1/4 of that of previously reported ICs. The dynamic range of a received signal strength indicator (RSSI) is 60 dB and the limited-output phase deviation is less than 7 deg. at 2 GHz. Therefore, this amplifier is quite suitable for single-conversion transceivers for broadband wireless access systems.

This correspondence reports novel computationally efficient algorithms for multiplication of bicomplex numbers, which belong to hypercomplex numbers. The proposed algorithms require less number of real multiplications than existing methods. Furthermore, they give more effective implementation when applied to constant coefficient digital filters.

We propose a hardware-based packet forwarder for multi-gigabit IP backbone networks. The conventional Internet deploys routers as a key block, but its software-controlled architecture makes it hard to scale up the packet forwarders, especially for table-lookup processes. We propose introducing a pure connectionless (CL) switching approach with a hardware-based forwarder to construct the core part of a scalable IP multi-gigabit backbone. Compared to a software-based forwarder, the table-lookup time is reduced to 100 ns by using content-addressable memory. This hardware-based pipeline implementation easily achieves a maximum forwarding performance of up to 9. 6-Gbps, or 23 million packets per second, for applications ranging from traditional best-effort IP applications to newly emerging time-critical ones. We also consider additional processing when transferring IP packets to enhance best-effort quality. This is done using selective packet-level discarding, including early packet discard and its enhancement, to achieve minimum bandwidth guaranteed service at the packet level. We discuss the IP backbone scalability issue from the viewpoint of new IP-forwarder technologies, paying special attention to connection-oriented (CO) vs. CL switching and hardware vs. software implementation. A pure CL switching solution consisting of a CL server (CLS) and a CL client (CLC) is proposed to balance the hardware- and software-based CL transport functions. As a first step to this solution, a compact CLS has been developed. It supports 600-Mbps throughput and up to 9. 6-Gbps forwarding power using a modular architecture. It was evaluated in an ATM field trial using an experimental network. The results show the effectiveness of our approach to providing enhanced best effort services.

The paper is focused on the architectural and technological solutions that will allow the transition from small to huge capacity ATM Switching Systems. This path starts from the industrial nodes available today and will arrive at the photonic switching architecture. The progressive introduction of photonics has already started with the use of optical interconnections in ATM nodes of hundreds of Gbit/s. A balanced use of microelectronics and photonics is the correct answer to the Terabit/s switching system challenge. After presenting a modular ATM Switching System, some technological solutions like Multichip Modules and Optical Interconnections are presented in order to explain how node capacity can be expanded. Some results of the research activity on photonic Switching are finally shown in order to exploit the great attitude of this technique to obtain very high throughput nodes.

Asynchronous Transfer Mode (ATM) networks are expected to support a diverse mix of traffic sources requiring different Quality Of Service (QOS) guarantees. This paper initially examines several existing scheduling disciplines which offer delay guarantees in ATM switches. Among them, the Earliest-Due-Date (EDD) discipline has been regarded as one of the most promising scheduling disciplines. The EDD discipline schedules the departure of a cell belonging to a call based on the delay priority assigned for that call during the call set-up. Supporting n delay-based service classes through the use of n respective urgency numbers D0 to Dn-1 (D0D1 Dn-1), EDD allows a class-i cell to precede any class-j (j>i) cell arriving not prior to (Dj-Di)-slot time. The main goal of the paper is to determine the urgency numbers (Dis), based on an in-depth queueing analysis, in an attempt to offer ninety-nine percentile delay guarantees for higher priority calls under various traffic loads. In the analysis, we derive system-time distributions for both high- and low-priority cells based on a discrete-time, single-server queueing model assuming renewal and non-renewal arrival processes. The validity of the analysis is justified via simulation. With the urgency numbers (Dis) determined, we further propose a feasible efficient VLSI implementation architecture for the EDD scheduling discipline, furnishing the realization of QOS guarantees in ATM switches.

Predicting the performance of high speed wide area ATM networks (WANs) is a difficult task. Evaluating the performance of these systems by means of mathematical models is not yet feasible. As a result, the creation of simulation models is usually the only means of predicting and evaluating the performance of such systems. In this paper, we use measurements to validate simulation models of TCP/IP over high speed ATM wide area networks. Validation of simulations with measurements is not common; however, it is needed so that simulation models can be used with confidence to accurately characterize the performance of ATM WANs. In addition, the appropriate level of complexity of the simulation models needs to be determined. The results show that under appropriate conditions simulation models can accurately predict the performance of complex high speed ATM wide area networks. This work also shows that the user perceived performance is dependent on host processing demands.

The symbol basis side information generated by Viterbi's ratio threshold test technique is proposed to improve the performance of the asynchronous slow-frequency-hopped multiple access system with BFSK signaling in the frequency non-selective fading channel. By properly setting the ratio threshold to produce erasure decisions for the received symbols, the system performances are optimized. The relationship among the hit symbols in a hop duration is exploited by this symbol basis side information to greatly reduce the packet error probability. This packet error rate improvement can be as large as two order of magnitude, compared with perfect hop basis side information systems.

Electroabsorption modulators are high speed devices that are rapidly being commercialised and finding applications in a number of areas, particularly in telecommunications. A CW laser diode modulated by an electroabsorption modulator constitutes an extremely stable, robust and simple source of high quality, high repetition rate ultrashort optical pulses. In this paper we describe the capabilities and limitations of such pulse sources, and present nonlinear pulse compression and manipulation techniques that allow one to overcome these limitations. We also present the design of a new class of comb-like dispersion-profiled fibre compressor. Such a compressor is easily fabricated from commercially available fibres and represents a simple yet powerful way of extending the range of pulse durations available. As the electroabsorption modulator is essentially a high speed switch it is also applicable to optical processing problems, and we report the application of such a device to demultiplexing.

Although the performance degradation for TCP/IP over plain ATM during congestion can be reduced if switch buffer management techniques such as Early Packet Discarding (EPD) and Partial Packet Discarding (PPD) schemes are employed. However, we show via simulation that fairness among connections remains a problem. For example, the fairness among packets of different length is a well known unsolved issue for EPD. To improve fairness of TCP and UDP over an Internet backbone, we propose a new technique called the Age Priority Packet Discarding (APPD) scheme to be used along with EPD and PPD. We employ two simulation scenarios to examine the performance of APPD; the MPEG-I video over UDP protocol and the FTP over TCP protocol. The simulation shows that with APPD combined with EPD and PPD, fairness can be well maintained against different packet length, order of connections, as well as different propagation delays. In addition, packet loss probability can be reduced with APPD in all scenarios, and the improvement is especially significant for video over UDP protocol. Finally we discuss the hardware implementation technique of the APPD scheme.

In the linear cryptanalysis (LC), to decrease the number of plain/cipher text pairs required for successful attack against DES, it is necessary to improve the effectiveness of the linear approximate expression and to decrease the number of key bits in the expression to be exhaustively searched for. In the previous work, we proposed a linear sieve method to improve the effectiveness of the linear approximate expression. On the other hand, the number of key bits increased. To suppress the number of key bits, we propose Fixed Sieve Linear Cryptanalysis (FS-LC) with fixed sieve key of the linear sieve method. With FS-LC against 8-round DES, we showed the number of plain/cipher text pairs required for sucessful attack is less than that of LC. Furthmore, we extended FS-LC with Kaliski's techniques using the multiple linear approximate expressions to intoroduce Fixed Sieve multiple Linear Cryptanalysis (FS-mLC). With FS-mLC against 8-round DES, computer simulation revealed that it is possible to solve its encryption-key with 220 plain/cipher text pairs. The number of pairs is about a half of the Matsui's 1-round linear cryptanalysis cases.

We propose a new method for verifying synchronous circuits using the Boyer-Moore Theorem Prover (BMTP) based on an efficient use of induction. The method contains two techniques. The one is the representation method of signals. Each signal is represented not as a waveform, but as a time parameterized function. The other is the mechanical transformation of the circuit description. A simple description of the logical connection of the components of a circuit is transformed into such a form that is not only acceptable as a definition of BMTP but also adequate for applying induction. We formalize the method and show that it realizes an efficient proof.

We present a new scheduling policy named Value-based Processor Allocation (VPA-k) for scheduling value-based transactions in a multiprocessor real-time database system. The value of a transaction represents the profit the transaction contributes to the system if it is completed before its deadline. Using VPA-k policy, the transactions with higher values are given higher priorities to execute first, while at most k percentage of the total processors are allocated to the urgent transactions dynamically. Through simulation experiments, VPA-k policy is shown to outperform other scheduling policies substantially in both maximizing the totally obtained values and minimizing the number of missed transactions.

A group-oriented cipher communication method is developed and implemented on a WWW-based (World Wide Web) network system. In this method, a group key common to all entities of the group is generated based on the group name or the identities of entities belonging to the group. The group key, in turn, is used for encrypting the data being shared among the group via the WWW server. The data theft at the WWW cache sites on the intermediate communication line is prevented, establishing a unified feature of the good WWW cache performance and security. A prototype of our method proved the feasibility and the efficiency.