In this paper, we illustrate the analysis of microstrip structures with a large number of unknowns using the sparse-matrix/canonical grid method. This fast Fourier thansform (FFT) based iterative method reduces both CPU time and computer storage memory requirements. We employ the Mixed-Potential Integral Equation (MPIE) formulation in conjunction with the RWG triangular discretization. The required spatial-domain Green's functions are obtained efficiently and accurately using the Complex Image Method (CIM). The impedance matrix is decomposed into a sparse matrix which corresponds to near interactions and its complementary matrix which corresponds to far interactions among the subsectional current elements on the microstrip structures. During the iterative process, the near-interaction portion of the matrix -vector multiplication is computed directly as the conventional MPIE formulation. The far-interaction portion of the matrix-vector multiplication is computed indirectly using fast Fourier transforms (FFTs). This is achieved by a Taylor series expansion of the Green's function about the grid points of a uniformly-spaced canonical grid overlaying the triangular discretization.

The integral kernel expansion method is applied to an analysis of scattering of magnetostatic forward volume waves (MSFVWs) by an array with any number of metal strips. In this method, first the integral kernel of the Fourier integral is expanded in terms of orthogonal polynomials to obtain moment equations. Then a system of algebraic equations is derived by applying the Galerkin's method. In the process, interaction between strips is naturally taken into account and real current distributions on the strips are determined such that boundary conditions are satisfied. Calculus confirmation through the energy conservation principle shows that numerical results are quite satisfactory. A comparison shows that theoretical results are in good agreement with experimental ones except the vicinity of lower and upper limits of the MSFVW band. It is shown that an infinite number of propagation modes is excited even if a wave of single mode is incident. Dependence of the scattering on dimension of arrays and on frequency and mode of an incident wave is obtained.

To reduce the memory access latency on sharedmemory multiprocessors, several prefetching schemes have been proposed. The sequential prefetching scheme is a simple hardware-controlled scheme, which exploits the sequentiality of memory accesses to predict which blocks will be read in the near future. Aggressive sequential prefetching prefetches many blocks on each miss to reduce the miss rates and results in good performance for application programs with high sequentiality. However, conservative sequential prefetching prefetches a few blocks on each miss to avoid prefetching of useless blocks, which shows better performance than aggressive sequential prefetching for application programs with low sequentiality. We analyze the relationship between the sequentiality of application programs and the effectiveness of sequential prefetching on various memory and network latency and propose a new adaptive sequential prefetching scheme. Simply adding a small table to the sequential prefetching scheme, the proposed scheme prefetches a large number of blocks for application programs with high sequentiality and reduces the miss rates significantly, and prefetches a small number of blocks for application programs with low sequentiality and avoids loading useless blocks.

In recently year, the analysis of power management becomes more important. It is difficult to obtain the maximum power because this is NP-complete. For an n-input circuit, there are 22n different input patterns to be considered. There are two major methods for this problem. First method is to generate input patterns to obtain the maximal power by simulating these generated patterns. This method is called pattern based. The other one uses probability method to estimate the power density of each node of a circuit to calculate the maximal power. In this paper, we use a pattern based method to estimate the maximal power. This method is better than that of probability for the simulation of power activity. In practical applications, these generated patterns can be applied and observe the activity of a circuit. These simulated data can be used to examined the critical paths for performance optimization. A simulated annealing algorithm is proposed to search input patterns for maximum power. Firstly, it transforms this problem into an optimization problem to adapt the simulated annealing method. In this method, there are three strategies for generating the next input patterns, called neighborhood. In the first strategy, it generates the next input pattern by changing the status of all input nodes. In the second strategy, some input nodes are selected and changed randomly.

This paper describes technological and operational issues of an image-art-on-demand system, which provides visitors with high-definition images of fine art in a virtual gallery. The system is presented as a typical example of multimedia information service systems on IP over ATM network. The high-definition images of fine arts from a database are interactively selected in a virtual gallery which is generated by an advanced computer graphics (CG) workstation. The generated images of the virtual gallery are transmitted by MPEG-2 over TCP/IP on ATM at 30 frames per second. This system was opened from January 1996 to March 1997 as one project of NTT's joint utilization tests of multimedia communications. As far as we know, this system is the first real-time image-art-on-demand system using MPEG-2 on IP over ATM-WAN to be exhibited to the general public.

Satellite beam-switching problems are studied where there are m up-link beams, n down-link beams and multiple carriers per beam. By augmenting a traffic matrix with an extra row and column, it is possible to find a sequence of switching modes ((0,1)-matrices with genrally multiple unit entries in each row and column) that realize optimal transmission time. Switching modes generated are shown to be linearly independent. The number of switching modes required for an mn matrix is bounded by (m1)(n1)1. For an augmented (m1)(n1) matrix, the bound is then mn1. The bounds on the number of switching modes and the computational complexity for a number of related satellite transmission scheduling problems are lowered. In simplified form, the results (particularly the linear independence of permutation matrices generated) apply to algorithmic decomposition of doubly stochastic matrices into convex combinations of permutation matrices.

Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

In this paper, we will show some significant results of the routability analysis of bit-serial pipeline datapath designs based on Rent's rule and Donath's observation. Our results show that all of the tested bit-serial benchmarks have Rent exponent of below 0.4, indicating that the average wiring length of the circuit is expected to be independent of the circuit size. This study provides some important implications on the silicon utilization and time-area efficiency of bit-serial pipeline circuits on FPGAs and ASICs.

A hybrid mo-demodulation approach, fully insensitive to the phase noise induced by the sources, is described for CDMA applications at optical frequencies. It is analytically demonstrated that, using bipolar codes in conjunction with polarisation modulation, the considered system can improve the performance of coherent schemes with not negligible laser linewidths, as well as the performance of more conventional noncoherent schemes based on intensity modulation and unipolar codes.

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.

In order to efficiently conduct the complex operations of network OpSs (Operation Systems), we introduce the TMN-based Integrated Management Display System (IMD). IMD is able to control the display of windows monitoring individual operations on multiple screens such as project monitors. In this paper, we describe an implementation of the IMD and experimental results. This implementation consists of the Multi-Screen Control System (MSS), Multi-Screen Agent System (MSA) and Multi-Screen Manager System (MSM). MSA controls MSS directly via proprietary protocols. MSM manages MSA via the TMN Interface. MSA is modeled using the GDMO (Guidelines for the Definition of Managed Objects). Moreover, in order to realize cooperation with other OpSs, MSM is based on TMN. We confirm that MSM interworks with ATMOS (ATM Transport Network Operation System) and develop an alarm surveillance system for ATMOS using IMD at in an OpS-Room. Experiments verify that MSA can be controlled by MSM following the alarms emitted from the real network equipment of the ATM Transport Network. As a result, the operators can comprehend the operations information more quickly than is possible with the conventional system. By using the TMN-based Integrated Management Display System (IMD), operations such as alarm surveillance can be performed more efficiently.

This paper presents an FPGA architecture for high-speed systems, such as next-generation B-ISDN telecommunications systems. Such a system requires an LSI in which an over-10K-gate circuit can be implemented and that has a clock cycle rate of 80MHz. So far, the FPGA architecture has only been discussed in terms of its circuit structure. In contrast we consider the circuit structure of the FPGA along with the performance of its dedicated CAD system. We evaluate several FPGA logic-element structures with a technology mapping method. From these experiments, a multiplexor-based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method. In addition, we examine how to best utilize the characteristics of the selected logic-cell structure in designing the wiring structure. It is found that the multiplexor-based cell can be connected efficiently in a clustered wiring structure.

A parallel IP router that uses off-the-shelf wor-kstations and interconnecting switches is presented. This router, called CORErouter-I, is a medium-grained, functionally distributed parallel system consisting of four kinds of processors for routing, routing-table searching, servicing, and line interfacing. Also discussed are issues related to the implementation of CORErouter-I, especially in terms of routing protocol processing and packet-forwarding. Performance characteristics of CORErouter-I are also clarified through several experiments performed to evaluate maximum throughput, analyze packet-forwarding time, and estimate the effect of parallel processing on the route-flapping problem.

In this paper, we propose an efficient solution for the Multiple Constant Multiplication (MCM) problem. The method uses hierarchical clustering to exploit common subexpressions among constants and reduces the number of shifts, additions, and subtractions. The algorithm defines appropriate weights, which indicate operation priority, and selects common subexpressions, resulting in a minimum number of local operations. It can also be extended to various high-level synthesis tasks such as arbitrary linear transforms. Experimental results for several error-correcting codes, digital filters and Discrete Cosine Transforms (DCTs) have shown the effectiveness of our method.

The dipole-dipole interaction among excitons is shown to give rise to an intrinsic nonlinearity, which yields a localized mode in a forbidden band, providing a coherent state for quantum computation. Employing this mode, a quantum XOR (exclusive OR) gate is proposed. A block structure of quantum dot arrays is also proposed, to implement quantum circuits comprising the quantum XOR gates for computation.

The multipass rendering method based on the global illumination model can generate the most photo-realistic images. However, since the multipass rendering method is very time consuming, it is impractical in the industrial world. This paper discusses a massively parallel processing approach to fast image synthesis by the multipass rendering method. Especially, we focus on the performance evaluation of the view-dependent object-space parallel processing on the (Mπ)2 which has been proposed in our previous paper. We also propose two kinds of distributed frame buffer system named cached frame buffer and multistage-interconnected frame buffer. These frame buffer systems can solve the access conflict problem on the frame buffer. The simulation results show that the (Mπ)2 has a scalable performance. For example, the (Mπ)2 with more than 4000 processing elements can achieve an efficiency of over 50%. We also show that both of the proposed distributed frame buffer systems can relieve the overhead due to frame buffer access in the (Mπ)2 in the case that a large number of high-performance processing elements are adopted in the system.

An implementation of photometric stereo is described in which all directions of illumination are close to and rotationally symmetric about the viewing direction. THis has practical value but gives rise to a problem that is numerically ill-conditioned. Ill-conditioning is overcome in two ways. First, many more than the theoretical minimum number of images are acquired. Second, principal components analysis (PCA) is used as a linear preprocessing technique to determine a reduced dimensionality subspace to use as input. The approach is empirical. The ability of a radial basis function (RBF) neural network to do non-parametric functional approximation is exploited. One network maps image irradiance to surface normal. A second network maps surface normal to image irradiance. The two networks are trained using samples from a calibration sphere. Comparison between the actual input and the inversely predicted input is used as a confidence estimate. Results on real data are demonstrated.

A novel approach to the cache coherent Multistage Interconnection Network (MIN) called the MINC (MIN with Cache control mechanism) is proposed. In the MINC, the directory is located only on the shared memory using the Reduced Hierarchical Bit-map Directory schemes (RHBDs). In the RHBD, the bit-map directory is reduced and carried in the packet header for quick multicasting without accessing the directory in each hierarchy. In order to reduce unnecessary packets caused by compacting the bit map in the RHBD, a small cache called the pruning cache is introduced in the switching element. The simulation reveals the pruning cache works most effectively when it is provided in every switching element of the first stage, and it reduces the congestion more than 50% with only 4 entries. The MINC cache control chip with 16 inputs/outputs is implemented on the LPGA (Laser Programmable Gate Array), and works with a 66 MHz clock.

Optical transmission systems with large capacity employing wavelength-division multiplexing (WDM) techniques are now widely under development. Optical amplifiers, especially Erbium-Doped Fiber Amplifiers (EDFA's), are vital components for such transmission systems. Optical amplifiers in WDM systems are employed as common amplifiers for all WDM'ed optical carriers, therefore, change in power of a specific carrier gives rise to gain fluctuation of the remaining carriers. In this paper, we discuss about automatic gain control (AGC) of EDFA for WDM'ed optical carriers under transient gain saturation. Two methods have been reported to perform AGC, i.e., pump feedback control method and compensation light feedback control method. Theory and experimental results have been already reported on pump feedback control method. Here, theory has been generalized to be applicable for compensation light feedback method including schematics with amplified spontaneous emission (ASE) as a probe light to measure the gain of EDFA. Experimental results have confirmed the analysis. Good performance has been obtained for both methods with simple electronic circuits and ASE has been found to work as an excellent probe light source.

This paper proposes a protocol to support mobility in the Internet with a new encapsulation technique. IP-squared (IP2). A basic idea to support mobility is as follows; 1) to define two IP addresses for each mobile host that indicate the host itself and its geographical location (logical and geographical identifiers), 2) to maintain an association of the logical identifier with the geographical identifier and 3) to continue communications between hosts by converting their logical identifiers to the corresponding geographical identifiers dynamically wherever they migrate. The association is called mobility binding. A goal of IP2 is to propose a mobility support feature which can simultaneously realize efficient routing paths to mobile hosts and less control traffics to maintain the mobility bindings into the current Internet Protocol without any modifications to both the conventional protocols and nodes. IP2 forms the efficient routing paths by enabling intermediate nodes to process the encapsulated datagrams. The key technique for this feature is a new header detection algorithm based on CRC checksum calculation and an effective usage of a header structure. Percentage of efficient routing paths can be adaptively controlled, depending on dispositions of the nodes which can en -and de capsulate datagrams appropriately based on the detection algorithm and the mobility bindings. The mobility binding must be updated whenever a mobile host migrates to another network. IP2 adopts an updating scheme combining self refreshment and on demand updating modes with taking a mechanism to form the efficient routing paths into considerations. It is shown that IP2 can acheive both an efficient routing path formation and a low traffic for mobility binding maintenance through analytical evaluations.