This paper describes the characteristics of a one dimensional narrow-wall slotted waveguide array with a single-layer linear-to-circular polarization converter consisting of a dipole array. An external boundary value problem of one slot and three dipoles, which approximates the mutual coupling between the dipole array and an edge slot extending over three faces of a rectangular waveguide, is formulated and analyzed by the method of moments; design of polarization conversion is conducted for this model as a unit element. If every unit element has perfect circular polarization, grating lobes appear in the array pattern due to the alternating slot angle: these are suppressed in this paper by changing the dipole angle and degrading the axial ratio of the unit element. The validity of the design is confirmed by the measurements. The dipole array has negligible effects upon slot impedance; the polarization conversion for existing narrow-wall slotted arrays is realized by add-on dipole array.

An analytic traffic model is presented to estimate the soft handoff rate in DS-CDMA cellular systems. The model is based on the fact that a mobile in soft handoff call is connected to two cell sites when it is in an overlapped region. The handoff rate is estimated by the mobility of mobiles, which is a function of the size and shape of cell area, and the call density and speed of mobiles in the area. Simulation results show good agreement with the analytical model.

The CROMACLEAR color display tube has been developed as a display that offers attractive icon quality and highly legible characters. The color display tube is composed of a striped superfine pitch phosphor screen with slot-type shadow mask. We explain the character legibility by Fourier transform. Moreover, the electron beam shape is improved. As a result, the CROMACLEAR color display tube has achieved higher legibility and lower moire phenomenon. This CROMACLEAR color display tube is already mounted in new monitor series.

High-speed display of 3-D objects in virtual reality environments is one of the currently important subjects. Shape simplification is considered an efficient method. This paper presents a method of hierarchical cube-based segmentation for shape simplification and multiresolution model construction. The relations among shape simplification, resolution and visual distance are derived firstly. The first level model is generated from scattered range data by cube-base segmentation with the first level cube size. Multiresolution models are then generated by re-sampling polygonal patch vertices of each former level model with hierarchical cube-based segmentation structure. The results show that the algorithm is efficient for constructing multiresolution models of free-form shape 3-D objects from scattered range data and high compression ratio can be obtained with little noticeable difference during the visualization.

In this paper, a systematic method which synthesizes the datapath of Application Specific Instruction Processor (ASIP) is proposed. The behavioral description of application is written in instruction code defined on abstract machine. We introduce register transfer graph (RTG) to represent instructions and synthesis constraint tree to select the combinations of synthesis constraints to explore design space along area and performance axis. The high performance is achieved by scheduling micro-operations of instruction in out-of-order. The practical datapath is synthesized by considering connection geometry as well as the maximum utilization of hardware resources. To reduce connection cost, data transfer paths are minimized by replacing an inefficient data transfer path with its bypass route. The feasibility of the proposed synthesis method is verified with several experimental instruction sequences.

In this paper, the evaluation of a hybrid acquisition performance has been considered for the pilot signal in direct sequence code division multiple access (DS/CDMA) forward link. The hybrid acquisition is introduced by the combination of two schemes, parallel and serial acquisitions. The mean acquisition time of the hybrid acquisition scheme is derived to consider both case 1 (the correct code-phase offsets ae included in one subset) and case 2 (the correct code-phase offsets exist at the boundary of two subsets), which are caused by the distribution of the correct code-phase offsets between two subsets. Detection, false alarm, and miss probabilities are derived for the cases of multiple correct code-phase offsets and multipath Rayleigh fading channel. Results are provided for the acquisition performance with respect to system design parameters such as postdetection integration length in the search and verification modes, subset size, and number of I/Q noncoherent correlators. Also, comparision between hybrid acquisition and parallel acquisition under the same hardware complexity is provided in terms of the minimum mean acquisition time.

This paper proposes a protocol to support mobile hosts in IPv6 by introducing a new addressing architecture and a new hop-by-hop option. This protocol also allows a mobile host to communicate with another host via a firewall machine which drops packets from untrustworthy hosts. The new addressing scheme is based on the separation of the identifier and the location of a mobile host. This is a straightforward implementation of the basic concept of VIP, a protocol providing seamless mobility in IPv4. The new hop-by-hop option of IPv6 allows a firewall machine to authenticate the source host of the forwarded packet with negligible overhead. The author plans to implement this protocol on several operating systems in the near future.

A new Neural Network Equalizer (NNE), employing multilayer feedforward neural network, is proposed as a compensation method for nonlinear and multipath distortion that arises from FTTA (Fiber To The Air) system. If a signal in a channel is affected by nonlinear distortion, the conventional Decision Feedback Equalizer (DFE) finds difficulty in perfect compensation of it. To compensate for nonlinear distortion as well as multipath distortion, an equalizer, employing neural network, is investigated. A new neural network equalizer, yielding a cubic function as unit output function, is proposed in order to compensate the nonlinear distortion effectively. We also propose an initial weights of neural network for preventing from local minimum. Computer simulation results show that the compensation performance of the new NNE is superior to the conventional DFE and the conventional NNE.

Overview of Cell Switch Router (CSR) and the CSR prototype system are described. CSR can simultaneously support both connection oriented IP flows and connectionless IP flows. CSR contains cell switch fabric and IP packet switch fabric to achieve high throughput IP forwarding. IP packets are forwarded either through a cut-thru packet transmission, in which packet are forwarded without reassembling IP packet nor IP header processing, or through a conventional hop-by-hop IP packet forwarding. This paper describes and proposes the mechanism to forward the connectionless IP packet flows at the CSR. A CSR prototype system has been developed. The CSR prototype system uses PVC connections to transfer the IP packets. With the CSR prototype system, we can make sure that CSR system can achieve a high throughput, i.e., 2.4 Gbps aggregated throughput. For end-to-end TCP/IP packet transmission, more than 90 Mbps can be achieved and realtime video transmission (30 Mbps video) can be achieved.

This paper proposes the reserved idle signal multiple access with collision resolution (R-ISMA/CR) protocol, which can maintain stability without being influenced by the retransmission probability. The R-ISMA/CR makes use of the multi-idle signals at the base station and the manipulating counter at the terminals. The performance of this protocol is evaluated by using the maximum throughput analysis and simulations.

This paper describes a new multiple DmB1C (Differential m Binary 1 Complement insertion) /DmB1M (Differential m Binary with 1 Mark insertion) coding scheme for high-speed optical multiplex transmission. The coding scheme has the characteristics of small consecutive identical digits and a good balance between marks and spaces. Furthermore, it has also good synchronization characteristics and higher flexibility for extension to high capacity transmission than the conventional mB1C or DmB1M coding schemes. We describe a design methodology for a multiplex transmission system using the proposed coding scheme, and verify the characteristics of the proposed coding scheme using an experimental setup of a 2.8 Gbit/s serial optical interconnection circuit, which has 16 parallel 156 Mbit/s inputs. The coding scheme realizes transmission systems with simple analog circuit configuration, and small digital circuit complexity with wide dynamic range and good mark ratio tolerance.

A digital neuro chip with proliferating neuron architecture is described. This chip simulates a neural network model called the adaptive segmentation of quantizer neuron architecture (ASQA). It has proliferating neurons, and can automatically form the optimum network structure for recognition according to the input data. To develop inexpensive commercial hardware and implement a proliferating neuron architecture, we adopt a virtual neuron system for hardware implementation. Namely, this chip is implemented with only an arithmetic unit for network computations, and the network information such as network structure, synaptic weights and so on, are stored in external memories. We devise our original architecture which can efficiently memorize the network information, and moreover, construct a structured network using the ASQA model. As a result, we can recognize about 3,000 Kanji characters using a single chip and a recognition speed of 4.6 msec/character is achieved on a PC.

This paper discusses the features of SOI/CMOS circuits in comparison with bulk/CMOS circuits. We have to design circuits with small fan outs and short wires to take advantage of high-speed and low-power SOI/CMOS devices to their fullest. We can take advantage of the SOI/CMOS structure if the ratio of the source/drain capacitances to the gate capacitances is much greater in the load capacitance. Thus, we propose a new flip-flop circuit with a smaller gate capacitance. The flip-flop circuit operates 30% faster than the previous circuit at 2.0 V. We also propose a buffer circuit having less delay disparity between the complementary output signals. The buffer circuit has the delay disparity of 18 ps at 0.2 pF and 2.0 V. We fabricated an 8-bit frequency divider and a 4-bit demultiplexer using the proposed circuits and 0.35 µm SOI/CMOS process. The 8-bit frequency divider and the 4-bit demultiplexer operate at 2.8 GHz and 1.6 GHz, respectively, at 2.0 V.

New functional surface tunnel transistors (STTs) with multiple interband-tunnel-junctions in a symmetric source-to-drain structure are proposed to reduce the number of fabrication steps and to increase functionality. These devices have p+/n+ interband tunnel junctions in series between a p+ source and a p+ drain through n+ channels. We successfully fabricated GaAs-based multiple-junction STTs (MJ-STTs) using molecular-beam epitaxy regrowth. This fabrication method eliminates the need for two of the photo-masks in the conventional process for asymmetric planar STTs. In the preliminary experiments using multiple-junction p+/n+ diodes, we found that the peak-voltage increment in negative-differential-resistance (NDR) characteristics due to the reverse-biased tunnel junction in negligible, while the first-peak voltage is roughly proportional to the number of forward-biased tunnel junctions. Moreover, the number of NDR characteristics are completely determined by the number of tunnel junctions. The fabricated STTs with multiple junctions, up to eight junctions, exhibited clear transistor operation with multiple NDR characteristics, which were symmetric with the drain bias. These results indicate that any number of gate-controlled NDR characteristics can be realized in MJ-STTs by using an appropriate number of tunnel junctions in series. In addition, as an example of a functional circuit using MJ-STTs, we implemented a tri-stable circuit with a four-junction STT and a load resistor connected in series. The tri-stable operation was confirmed by applying a combination of a reset pulse and a set pulse for each stable point.

A new multiple-valued current-mode (MVCM) integrated circuit using a switched current-source control technique is proposed for a 1.5 V-supply high-speed arithmetic circuit with low-power dissipation. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using a switched current control technique, the static power dissipation can be greatly reduced because current sources in non-active circuit blocks are turned off. Since the gate of each current source is directly controlled by using a multiphase clock whose technique has been already used in dynamic circuit design, no additional transistors are required for currentsource control. As a typical example of arithmetic circuits, a new 1.5 V-supply 5454-bit multiplier based on a 0.8µm standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the proposed MVCM integrated circuit.

Experimental demonstrations of IP over ATM with congestion avoidance flow control are described. The results confirm that this network can control the transmission rate without upper layer anomalies, IP packet loss, or TCP retransmission. Efficient and fair sharing of the available bandwidth is realized in local area networks.

The Resource Auction Multiple Access (RAMA) protocol was proposed by N. Amitay for fast resource allocations to mobile terminals. We have proposed an Enhanced RAMA (ERAMA) protocol yielding lower system delay and delay variations than does the RAMA protocol. In this paper, we model a two-stage queueing network to evaluate the performance of the proposed protocol in terms of mean access delay, mean buffering delay, talk spurt loss ratio, and channel utilization, under homogeneous voice connections. The analytical results yield upper estimates for the various performance indices, compared with those of the simulations.

This paper provides an architectural study of optical multiple-ring trunk-transmission networks using high-speed Time Division Multiplexing (TDM), and proposes two algorithms for distributed control environments. We propose a path-setup algorithm that uses Token protocol over Section Overhead (SOH) bytes, by which network-nodes communicate with each other to reserve bandwidth. A classified path restoration algorithm is also proposed that offers 3 path classes in terms of restoration performance. Class A paths, the most reliable, never lose any bit even against unpredictable disasters. They are realized by path-duplication at the source node, route diversity,and hitless switching at the destination node. Class B paths are restored by re-routing, where the original path-setup algorithm is reused. Class C paths are the most economical because a failed path is restored by maintenance action.

This work presents a further development of the approach to modelling thermal (i.e. carrier-velocity-fluctuation) noise in semiconductor devices proposed in papers by the present authors. The basic idea of the approach is to apply classical theory of Ito's stochastic differential equations (SDEs) and stochastic diffusion processes to describe noise in devices and circuits. This innovative combination enables to form consistent mathematical basis of the noise research and involve a great variety of results and methods of the well-known mathematical theory in device/circuit design. The above combination also makes our approach completely different, on the one hand, from standard engineering formulae which are not associated with any consistent mathematical modelling and, on the other hand, from the treatments in theoretical physics which are not aimed at device/circuit models and design. (Both these directions are discussed in more detail in Sect. 1). The present work considers the bipolar transistor compact model derived in Ref. [2] according to theory of Ito's SDEs and stochastic diffusion processes (including celebrated Kolmogorov's equations). It is shown that the compact model is transformed into the Ito SDE system. An iterative method to determine noisy currents as entries of the stationary stochastic process corresponding to the above Ito system is proposed.

This paper explores the potential of multiwave interconnectionsoptical interconnections that employ wavelength components as multiplexable information carriersfor constructing next-generation multiprocessor systems using MCM technology. A hypercube-based multiprocessor network called the multiwave hypercube (MWHC) is proposed, where multiwave interconnections provide highly-flexible dynamic communication channels among processing elements. A performance analysis shows that the use of multiwavelength optics makes possible the reduction of network complexity on an MCM substrate, while supporting low-latency message routing.