This paper proposes a design method of feature spaces in a two-stage image recognition method that improves the recognition accuracy and efficiency in statistical image recognition. The two stages are (1) image screening and (2) image recognition. Statistical image recognition methods require a lot of calculations for spatially matching between subimages and reference patterns of the specified objects to be detected in input images. Our image screening method is effective in lowering the calculation load and improving recognition accuracy. This method selects a candidate set of subimages similar to those in the object class by using a lower dimensional feature vector, while rejecting the rest. Since a set of selected subimages is recognized by using a higher dimensional feature vector, overall recognition efficiency is improved. The classifier for recognition is designed from the selected subimages and also improves recognition accuracy, since the selected subimages are less contaminated than the originals. Even when conventional recognition methods based on linear transformation algorithms, i. e. principal component analysis (PCA) and projection pursuit (PP), are applied to the recognition stage in our method, recognition accuracy and efficiency may be improved. A new criterion, called a screening criterion, for measuring overall efficiency and accuracy of image recognition is introduced to efficiently design the feature spaces of image screening and recognition. The feature space for image screening are empirically designed subject to taking the lower number of dimensions for the feature space referred to as LS and the larger value of the screening criterion. Then, the recognition feature space which number of dimensions is referred to as LR is designed under the condition LSLR. The two detection tasks were conducted in order to examine the performance of image screening. One task is to detect the eye- and-mouth-areas in a face image and the other is to detect the text-area in a document image. The experimental results demonstrate that image screening for these two tasks improves both recognition accuracy and throughput when compared to the conventional one-stage recognition method.

In the linear cryptanalysis (LC), to decrease the number of plain/cipher text pairs required for successful attack against DES, it is necessary to improve the effectiveness of the linear approximate expression and to decrease the number of key bits in the expression to be exhaustively searched for. In the previous work, we proposed a linear sieve method to improve the effectiveness of the linear approximate expression. On the other hand, the number of key bits increased. To suppress the number of key bits, we propose Fixed Sieve Linear Cryptanalysis (FS-LC) with fixed sieve key of the linear sieve method. With FS-LC against 8-round DES, we showed the number of plain/cipher text pairs required for sucessful attack is less than that of LC. Furthmore, we extended FS-LC with Kaliski's techniques using the multiple linear approximate expressions to intoroduce Fixed Sieve multiple Linear Cryptanalysis (FS-mLC). With FS-mLC against 8-round DES, computer simulation revealed that it is possible to solve its encryption-key with 220 plain/cipher text pairs. The number of pairs is about a half of the Matsui's 1-round linear cryptanalysis cases.

This paper is concerned with CDMA applied to personal and mobile communications on a global basis using multiple low earth orbital satellites (LEOS). We focus our attention on some unique aspects of LEOS systems and discuss their influences on the CDMA system performance as well as the techniques for coping with these aspects. We deal with three kinds of important items that are unique to LEOS systems; Doppler frequency shift due to satellite movement, propagation delay affecting packetized data transmission and geographical nonunifomity in traffic.

Pre-decorrelation is a method of achieving orthogonalization between multiple signals on the forward link. This technique can achieve orthogonalization in a flat fading channel, however, the orthogonality does not clearly appear in a multipath fading channel because of interchip interference. In order to eliminate the effect of multipath and prevent interchip interference, multicarrier modulation can be employed. In this paper we propose a multicarrier pre-decorrelation technique which combines multicarrier modulation with pre-decorrelation. Computer simulation results show that the proposed technique can achieve orthogonalization in a multipath fading channel.

A 100MIPS high speed and low power fixed point Digital Signal Processor (DSP) has been developed applying 0.45µm CMOS TLM technology. The DSP contains a 16-bit32K full CMOS static RAM with a hierarchical low power architecture. The device is a RAM based DSP with a total of 4.2 million transistors and a new low power design and process which enabled an approximate 50% reduction in power as compared to conventional DSPs at 40 MHz. In order to cover very wide application requirements, this DSP is capable of operating at 1.0 V for DSP core and 3.3 V for I/O. This was achieved by new level shifter circuitry to interface with cost effective 3 V external commodity products and confirmed 80% of power reduction at Core VDD=2.0 V, I/O VDD=3.3 V at 40MHz. This paper describes the new features of the high speed and low power DSP.

We have developed an efficient recursive algorithm based on the interacting multiple model (IMM) for enhancing speech degraded by additive white noise. The clean speech is modeled by the hidden filter model (HFM). The simulation results shows that the proposed method offers performance gains relative to the previous one with slightly increased complexity.

In this paper, a simple frame synchronization system for M-ary Spread Spectrum (M-ary/SS) communication system is analyzed. In particular, synchronization performance, bit error rate performance, and Spread Spectrum Multiple Access (SSMA) performance are analyzed. The frame synchronization system uses the racing counters. The transmitted signal contains framing chips that are added to spreading sequences. In the receiver, the framing chips are detected from several frames. The authors have proposed the simple frame synchronization system that detects framing chips from consecutive 2 frames. In this system, as the number of framing chips increases, synchronization performance improves and bit error rate performance degrades. In this paper a frame synchronization system that improves bit error rate performance is treated and analyzed. As the rusult, when the number of reference frames is 3, the bit error rate is much improved than the conventional system.

In addition to additive thermal noise, a received direct-sequence spread spectrum (DS/SS) signal may suffer from intersymbol interference (ISI) and interference caused by cochannel narrowband users or other narrowband radio frequency interference (RFI). This paper presents a workable solution for removing narrowband interference (NBI) and reducing ISI or inter-chip interference (ICI) when the communication channel can be modeled as an FIR filter and the NBI comes from multiple CW tones, an AR-modeled Gaussian process, or a BPSK signal. Unlike earlier solutions, the proposed scheme is capable of performing the functions of NBI-rejection, ISI/ICI suppression and data detection (code despreading) simultaneously. It is easy to implement and, more importantly, it yields lower bit error rate (BER) and smaller mean squared error (MSE).

This paper surveys low-power design techniques for Si bipolar Gbit/s LSIs. First, a total strategy for power reduction in bipolar LSIs is described. The power dissipation of Si bipolar LSIs can be minimized by reducing the supply voltage, switching and driving currents, the power of input and output circuits, and the equivalent "on" ratio. Widely spread activities from device to architecture levels are indispensable and each of the low-power techniques reduces power by a factor of about 0.5 to 0.7. The integration of these techniques is very important, and as a certain example of their effectiveness, an SOH signal processing LSI is demonstrated with a reduction factor of 1/10. Comparisons with other device technologies for low power characteristics reveal the low-power potential of bipolar LSIs in the Gbit/s region.

This paper proposes a novel synchronous acquisition method with an adaptive filter in asynchronous direct sequence/code division multiple access (DS/CDMA) communication systems. An adaptive filter is used in a single-user receiver, in complete synchronization of desired user's signal, the tap coefficients of the filter are controlled to orthogonalize to all other user's spreading sequences without knowledge of the sequences, amplitude and time delays of the signals. While, in the proposed system for synchronous acquisition, the tap coefficients are controlled to orthogonalize to all user's sequences including desired user's signal. The synchronous acquisition can be achieved by using the difference of cross-correlation function value between desired user's sequence of inphase and the tap coefficients for each phase. The principle and performance evaluation for the proposed method are shown. As a result, compared to an acquisition method of conventional sliding correlator, considerable improvement of the average acquisition time can be achieved in large power multiple access interference environment.

In this paper, three issues concerning the linear adaptive receiver using the LMS algorithm for single-user demodulation in direct-sequence/code-division multiple-access (DS/CDMA) systems are considered. First, the convergence rate of the LMS algorithm in DS/CDMA environment is considered theoretically. Both upper and lower bounds of the eigenvalue spread of the autocorrelation matrix of receiver input signals are derived. It is cleared from the results that the convergence rate of the LMS algorithm becomes slow when the signal power of interferer is large. Second, fast converging technique using a prefilter is considered. The LMS based adaptive receiver using an adaptive prefilter adjusted by a Hebbian learning algorithm to decorrelate the input signals is proposed. Computer simulation results show that the proposed receiver provides faster convergence than the LMS based receiver. Third, the complexity reduction of the proposed receiver by prefiltering is considered. As for the reduced complexity receiver, it is shown that the performance degradation is little as compared with the full complexity receiver.

This paper describes the 10-bit 50 MS/s pipelined CMOS A/D Converter using a "reference feed-forward architecture." In this architecture, reference voltage generated in a reference generator block and residual voltage from a DA/subtractor block are fed to the next stage. The reference generator block and DA/subtractor block are constructed using resistive-load, low-gain differential amplifiers. The high-gain, high-speed amplifiers consuming much power are not used. Therefore, the power consumption of this ADC is reduced. The gain matching of the reference voltage with the internal signal range is achieved through the introduction of the reference generator block having the same characteristics as a DA/subtractor block. Each offset voltage of the differential amplifier in the reference generator block and the DA/subtractor block is canceled by the offset cancellation technique, individually. In addition, the front-end sample/hold circuit is eliminated to reduce power consumption. Because of the introduction of high-speed comparators based on the source follower and latch circuit into the first stage A/D subconverter, analog bandwidth is not degraded. This ADC has been fabricated in double-polysilicon, double-metal, 0.5µm CMOS technology, and it operates at 50 MS/s with a 300-mW (Vdd=3.0 V) power consumption. The differential linearity error of less than +/-1 LSB is obtained.

The advantages of DRAM-logic integration were demonstrated through a comparison with a conventional separate-chip architecture. Although the available DRAM capacity is restricted by chip size, the integration provides a high throughput and low I/O-power dissipation due to a large number of on-chip I/O lines with small load capacitance. These features result in smaller chip counts as well as lower power dissipation for systems requiring high data throughput and having relatively small memory capacity. The chip count and I/O-power dissipation were formulated for multimedia systems. For the 3-D computer graphics system with a frame of 12801024 pixels requiring a 60-Mbit memory capacity and a 4.8-Gbyte/s throughput, DRAM-logic integration enabled a 1/12 smaller chip count and 1/10 smaller I/O-power dissipation. For the 200-MIPS hand-held portable computing system that had a 16-Mbit memory capacity and required a 416-Mbyte/s throughput, DRAM-logic integration enabled a 1/4 smaller chip count and 1/17 smaller I/O-power dissipation. In addition, innovative architectures that enhance the advantages of DRAM-logic integration were discussed. Pipeline access for a DRAM macro having a cascaded multi-bank structure, an on-chip cache DRAM, and parallel processing with a reduced supply voltage were introduced.

A computer-aided low-power design methodology for very high-speed Si bipolar standard cell LSI is described. In order to obtain Gbit/s-speed operation, it features a pair of differential clock channels inside cells and a highly accurate static timing analysis for back annotation. A newly developed CAD-based power optimization scheme minimizes cell currents while maintaining circuit speed. A 5.6 k gate SDH signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design technology.

An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.

A method for analyzing the scattering of electromagnetic waves by a general bianisotropic slab is presented by extending the author's previous approaches for anisotropic, chiral, and those periodic media. The analysis is formulated in a unified matrix form, so that scattering characteristics can be obtained by system matrix calculations. The method can be extended straightforwardly to multilayerd and periodic structures. The scattering efficiencies are obtained for the incidence of not only linearly polarized waves but also circularly polarized waves.

Three-dimensional (3-D) instrumentation using an image sequence is a promising instrumentation method for intelligent systems in which accurate 3-D information is required. However, real-time instrumentation is difficult since much computation time and a large memory bandwidth are required. In this paper, a 3-D instrumentation VLSI processor with a concurrent memory-access scheme is proposed. To reduce the access time, frequently used data are stored in a cache register array and are concurrently transferred to processing elements using simple interconnections to the 8-nearest neighbor registers. Based on a row and column memory access pattern, we propose a diagonally interleaved frame memory by which pixel values of a row and column are stored across memory modules. Based on the concurrent memory-access scheme, a 40 GOPS vprocessor is designed and the delay time for the instrumentation is estimated to be 42 ms for a 256256 images.

This paper presents a method of analyzing the electromagnetic field inside an equipment housing. The electromagnetic field is assumed to be coming from outside and coupled into the housing through an aperture on the housing surface. The analysis is based on the transmission-line modeling method. Results of the analysis show a good agreement with the results of measurement. Also, it is found that the coupling through the aperture shows peaks at some frequencies that depend almost only on the structure of the housing and aperture and, therefore, can be estimated at the time of equipment design.

In this paper, we illustrate the analysis of microstrip structures with a large number of unknowns using the sparse-matrix/canonical grid method. This fast Fourier thansform (FFT) based iterative method reduces both CPU time and computer storage memory requirements. We employ the Mixed-Potential Integral Equation (MPIE) formulation in conjunction with the RWG triangular discretization. The required spatial-domain Green's functions are obtained efficiently and accurately using the Complex Image Method (CIM). The impedance matrix is decomposed into a sparse matrix which corresponds to near interactions and its complementary matrix which corresponds to far interactions among the subsectional current elements on the microstrip structures. During the iterative process, the near-interaction portion of the matrix -vector multiplication is computed directly as the conventional MPIE formulation. The far-interaction portion of the matrix-vector multiplication is computed indirectly using fast Fourier transforms (FFTs). This is achieved by a Taylor series expansion of the Green's function about the grid points of a uniformly-spaced canonical grid overlaying the triangular discretization.

The integral kernel expansion method is applied to an analysis of scattering of magnetostatic forward volume waves (MSFVWs) by an array with any number of metal strips. In this method, first the integral kernel of the Fourier integral is expanded in terms of orthogonal polynomials to obtain moment equations. Then a system of algebraic equations is derived by applying the Galerkin's method. In the process, interaction between strips is naturally taken into account and real current distributions on the strips are determined such that boundary conditions are satisfied. Calculus confirmation through the energy conservation principle shows that numerical results are quite satisfactory. A comparison shows that theoretical results are in good agreement with experimental ones except the vicinity of lower and upper limits of the MSFVW band. It is shown that an infinite number of propagation modes is excited even if a wave of single mode is incident. Dependence of the scattering on dimension of arrays and on frequency and mode of an incident wave is obtained.