This letter examines outline measures of strength against the differential and linear cryptanalysis. These measures are useful to estimate the number of rounds giving an immune iterated cipher. This letter reports that the outline measures of strength are useful to relatively estimate the strength of generalized feistel ciphers.

We have developed a Field-Programmable Multi-Chip Module (FPMCM) whose component is the telecommunication-oriented FPGAs, called PROTEUS. The module consists of 3 3 PROTEUS FPGAs and its size is 114 mm square. Each PROTEUS chip is mounted on the MCM substrate using Tape Automated Bonding (TAB) technology so as to minimize the size of the MCM and the production cost. The interconnection topology among the FPGAs is a simple mesh. However, the connection can be changed logically, because PROTEUS itself has a special inter-I/O bypass resource in it. Using this mechanism, the interchip connection delay can be reduced without sacrificing the flexibility, compared to the previous FPMCM implementation using some other interconnection switches which often have a large propagation delay. The interchip connection delay is 200 ps. We have also developed a rapid prototyping system comprising several MCMs, and implemented telecommunication circuits in it.

This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.

Providing various assistances for design modifications on HDL source codes is important for design reuse and quick design cycle in VLSI CAD. Program slicing is a software-engineering technique for analyzing, abstracting, and transforming programs. We show algorithms for extracting/removing behaviors of specified signals in VHDL descriptions. We also describe a VHDL slicing system and show experimental results of efficiently extracting components from VHDL descriptions.

This paper experimentally confirms the throughput characteristics of TCP and Network Direct Memory Access (Network DMA), our proposed data transfer protocol, over a large delay-band-width link. The experiments clarify that the various problems of TCP over large delay-bandwidth links include limited window size, data retransmission mechanism, and protocol processing overhead. The test results suggest that we must improve not only protocol itself but also the protocol processing architecture to realize Gbit/s class throughput over such links. To avoid these problems, Network DMA realizes high speed memory copy across a network by labeling each packet with its memory address without host CPU intervention; protocol processing is done by firmware on the network interface card. Moreover, it realizes selective retransmission by using the memory addresses. Test results show that Network DMA achieves the sustained throughput of 535Mbit/s over a 10,000km 622Mbit/s ATM link and over 400Mbit/s effective throughput even when the cell loss ratio is 10-4.

In this paper, we present an analysis of the microstrip lines whose strip conductors are of various cross-sections, such as rectangular cross-section, triangle cross-section, and half-cycle cross-section. The method employed is the boundary integral equation method (BIEM). Numerical results for these microstrip lines demonstrate various shape effects of the strip conductor on the characteristics of lines. The processing technique on the convergence of the Green's function is also described.

This paper describes a method to represent m output functions using shared multi-terminal binary decision diagrams (SMTBDDs). The SMTBDD(k) consists of multi-terminal binary decision diagrams (MTBDDs), where each MTBDD represents k output functions. An SMTBDD(k) is the generalization of shared binary decision diagrams (SBDDs) and MTBDDs: for k=1, it is an SBDD, and for k=m, it is an MTBDD. The size of a BDD is the total number of nodes. The features of SMTBDD(k)s are: 1) they are often smaller than SBDDs or MTBDDs; and 2) they evaluate k outputs simultaneously. We also propose an algorithm for grouping output functions to reduce the size of SMTBDD(k)s. Experimental results show the compactness of SMTBDD(k)s. An SMTBDDmin denotes the smaller SMTBDD which is either an SMTBDD(2) or an SMTBDD(3) with fewer nodes. The average relative sizes for SBDDs, MTBDDs, and SMTBDDs are 1. 00, 152. 73, and 0. 80, respectively.

The influence of loaded capacitance on the resonant frequency of a triplate-type strip resonator is investigated through numerical simulations by means of the finite-difference time-domain (FDTD) method. This type of resonator is one of the basic components of very small high-dielectric stripline filters, named laminated planar filters. Numerical results of resonant frequencies are compared with experimental results and found to be in excellent agreement, which circumstance ensures that the FDTD method can be applied to the characterization of a wide range of laminated planar microwave devices including resonators and filters. It is also found that the resonant frequency is directly related to the square root of its line capacitance when the resonator is regarded equivalently as a series LC circuit.

This paper studies the application of a media synchronization mechanism to the interleaved transmission of video and audio specified by the H.223 Annex in PHS. The media synchronization problem due to network delay jitters in the interleaved transmission has not been discussed in either the Annex or any related standards. The slide control scheme, which has been proposed by the authors, is applied to live media. We also propose a QOS control scheme to control both quality of the media synchronization and that of the transmission delay. Through simulation we confirm the effectiveness of the slide control scheme and the QOS control scheme in the interleaved transmission.

This paper proposes a novel signal transmission scheme for helicopter satellite communications. The proposed scheme is based on time diversity, and combined with a novel algorithm to suppress an influence of carrier phase slip. In the proposed scheme, carrier phase slip is detected in cross correlation processing of the received signal, and is effectively suppressed. The proposed scheme thus makes it possible to employ coherent phase shift keying modulation to achieve bit error rate performance superior to that of differential phase shift keying modulation even in the low carrier-to-noise power ratio environment.

This paper proposes a new flexible hardware model for pipelined design optimization. Using together with an RTL floorplanner, the flexible hardware model makes accurate and fine design space exploration possible. It is quite effective for deep submicron technology since estimation at high level has become a difficult problem and the design tuning at lower level of abstraction makes up the full design optimization task. The experimental results show that our approach reduces the slack time in the pipeline stages then achieves higher performance with a smaller area.

In recent years, several global network systems using non-stationary satellites have been proposed. Some of them are announced to start services within years. We also have several experimental systems with stratospheric aircrafts. In the future, the radio communication system using stratospheric aircrafts will be one of the promising media for personal communications. The question of how to establish the optimal communication under such circumstance seems to be still open. In this paper, performance evaluations of wireless communication systems using LEO satellites and stratospheric aircrafts are proposed. We will show some proper communication parameters to improve competence of mobile communication in the such systems as well.

In designing ASIPs (Application Specific Integrated Processors), the papers investigated so far have almost focused on the optimization of the CPU core and did not pay enough attention to the optimization of the RAM and ROM sizes together. This paper overcomes this limitation and proposes an optimization algorithm to define the best ratio between the CPU core, RAM and ROM of an ASIP chip to achieve the highest performance while satisfying design constraints on the chip area. The partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and software so that the performance of the designed ASIP is maximized under given chip area constraint, where the chip area includes the HW cost of the register file for a given application program with associated input data set. The optimization problem is parameterized so that it can be applied with different technologies to synthesize CPU cores, RAMs or ROMs. The experimental results show that the proposed algorithm is found to be effective and efficient.

We describe a new multiport memory which is called Shared DRAM (SHDRAM) to overcome bus-bottle neck problem in parallel processor system with shared memory. The processors are directly connected to this SHDRAM without conventional common bus. The test chip with 32 kbit memory cells is fabricated using a 1. 5 µm CMOS technology. The basic operation is confirmed by the circuit simulation and experimental results. In addition, it is confirmed by the computer simulation that the system performance with SHDRAM is superior to that with conventional common buses.

When wireless multi-media information such as voice, video, data and so on are transmitted, the difference required quality of Service (QoS) including required Bit Error Rate (BER), required information bit rate, message's delay constraints as well as traffic performance should be taken into account. A wireless multi-media system should achieve a flexible balance of these differences. In this letter, an Adaptive Chip/Bit Control Method is proposed for Wireless Multi-media CDMA System. The proposed method controls both chip and bit rate of each medium according to the offered traffic condition and the quality measurement of each medium. In the proposed method, measurement are carried out in the base station. Simulation results show that the proposed method not only maintain the required BER of each medium, but achieve a higher total throughput even in high traffic condition. Thus we see that the proposed method possesses higher flexible ability than conventional methods.

We have proposed a highly scattering optical transmission (HSOT) polymer for use as a high efficiency light source medium. This polymer contains specified internal microscopic heterogeneous structures for controlling light-transmission properties. An LCD backlighting system having a new light pipe made of this polymer has twice the brightness of the conventional one. A light scattering phenomenon inside the HSOT polymer was quantitatively analyzed by a ray tracing simulation based on the Mie scattering theory and the Monte Carlo method. The illumination of the backlight which is optimized by using the simulation program has enough uniformity of intensity and color because of specified multiple light scattering phenomena inside the HSOT polymer. We propose the new backlighting system having fewer components and twice efficiency of the conventional one.

This paper proposes a novel asynchronous direct sequence/code division multiple access (DS/CDMA) communication system using analog pseudo noise (PN) sequences that have an orthogonal relation for all active users. Analog PN sequences are produced by an adaptive filter called a "code-orthogonalizing filter" (COF). In a base station receiver, the tap coefficients of the COF can be adaptively controlled "to orthogonalize" or "to approach to orthogonalize" various received PN sequences. The elements of the analog PN sequences consist of the tap coefficients of the COF. The analog PN sequence produced is assigned to the transmitter of each user in order. As a result, multiple access interference (MAI) caused by other users can be reduced considerably, and multiple access capacity increased by the proposed system compared with matched filter (MF) reception and COF reception.

This paper proposes a scalable multiecho cancellation system based on multiple autonomic and distributed echo canceler units. The proposed system does not have any common control section. Distributed control sections are equipped with in multiple echo cancelers operating autonomically. Necessary information is transferred from one unit to the next one. When the number of echoes to be canceled is changed, the necessary number of echo canceler units, each of which may be realized on a single chip, are simply plugged in or unplugged. The proposed system also provides fast convergence thanks to the novel coefficient location algorithm which consists of flat-delay estimation and constrained tap-position control. The input signal is evaluated at each tap to determine when to terminate flat-delay estimation. The number of exchanged taps is selected larger in flat-delay estimation than in constrained tap-position control. The convergence time with a colored-signal input is reduced by approximately 50% over STWQ, and 80% over full-tap NLMS algorithm. With a real speech input, the proposed system cancels the echo by about 20 dB. Tap-positions have been shown to be controlled correctly.

In this paper, the bit error rate (BER) performance of the Spread Spectrum communication with Constrained Spreading Code system is studied under the synchronous CDMA system. Particularly, BER considering the tracking error is derived by theoretical analysis. The synchronizing spreading sequence is employed to track the signals in the receiver. As the result, the BER performance is degraded by increasing the number of users. However, the BER performance can be improved by canceling the co-channel interference and by suppressing the cross-correlation value between the information spreading sequence and the synchronizing spreading sequence.

In this paper, a novel pass-transistor logic with an efficient level restoration circuit, named Power Saved Pass-transistor Logic (PSPL), is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of PSPL, a 5454-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth Encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13. 5 ns in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. Furthermore, a sequential circuit of a low power 7-bit serial counter is designed and fabricated in a 0. 6 µm single-poly triple-metal 3. 3 V CMOS process. The measured operating speed was 250 MHz.