Photonic integrated circuits (PICs) are required for future optical communication systems, because various optical components need to be compactly integrated in one-chip configurations with a small number of optical alignment points. Bandgap energy controlled selective metal organic vapor phase epitaxy (MOVPE) is a breakthrough technique for the fabrication of PICs because this technique enables the simultaneous formation of waveguides for various optical components in one-step growth. Directly formed waveguides on a mask-patterned substrate can be obtained without using conventional mesa-etching of the semiconductor layers. The waveguide width is precisely controlled by the mask pattern. Therefore, high device uniformity and yield are expected. Since we proposed and demonstrated this technique in 1991, various PICs have been reported. Using electroabsorption modulator integrated distributed feedback laser diodes, 2.5 Gb/s-550 km transmission experiments have been successfully conducted. Another advantage of the selective MOVPE technique is the capability to form narrow waveguide layers. We have demonstrated a polarization-insensitive semiconductor optical amplifier that consists of a selectively formed narrow (less than 1 µm wide) bulk active layer. For a four-channel array, a chip gain of more than 20 dB and a gain difference between TE and TM inputs of less than 1 dB were obtained. We have also reported an optical switch matrix and an optical transceiver PIC for access optical networks. By using a low-loss optical waveguide, a 0 dB fiber-to-fiber gain for the 14 switch matrix and 0 dBm fiber output power from the 1.3 µm transceiver PIC were obtained. In this paper, the selective MOVPE technique and its applications to various kinds of PICs are discussed.

Wavelength Division Multiplexing (WDM) technology provides many options to the design of flexible alloptical networks. To exploit these options to their full potential, Photonic Integrated Circuits (PICs) for wavelength routing and switching will be indispensable. One of the basic building blocks of such PICs is the planar phased-array (PHASAR) wavelength demultiplexer. The monolithic integration of PHASARs with photodetectors, amplifiers, and other waveguide-based (passive) components is discussed.

Silica-based planar lightwave circuits (PLCs) are reviewed in terms of WDM applications. Four types of basic multiplexer are described and compared. Some topical applications of these multiplexers are introduced with their WDM systems. We conclude that because of these various applications, silica-based PLCs will play an important role in future WDM systems.

A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 1616 (256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.

This paper reviews recent developments in small-sized broadband antennas for EMI measurements, especially in the microwave frequency region. Transient EMI measurements are also discussed by introducing complex antenna factors and conversion of frequency-domain data into time-domain data. This paper also focuses on considerable improvements achieved in calibration techniques for conventional EMI antennas in VHF/UHF bands.

This paper optimizes a hierarchical image transmission system based on the hierarchical modulation scheme in a band-limited Rayleigh fading channel. Authors analyze relations between hierarchical parameters and the image quality, and show that the existence of optimum hierarchical parameter that maximizes the received image quality.

We present a very fast method for calculating an inverse filter for audio reproduction system. The proposed method of FFT-based inverse filter design, which combines the well-known principles of least squares optimization and regularization, can be used for inverting systems comprising any number of inputs and outputs. The method was developed for the purpose of designing digital filters for multi-channel sound reproduction. It is typically several hundred times faster than a conventional steepest descent algorithm implemented in the time domain. A matrix of causal inverse FIR (finite impulse response) filters is calculated by optimizing the performance of the filters at a large number of discrete frequencies. Consequently, this deconvolution method is useful only when it is feasible in practice to use relatively long inverse filters. The circular convolution effect in the time domain is controlled by zeroth-order regularization of the inversion problem. It is necessary to set the regularization parameter β to an appropriate value, but the exact value of β is usually not critical. For single-channel systems, a reliable numerical method for determining β without the need for subjective assessment is given. The deconvolution method is based on the analysis of a matrix of exact least squares inverse filters. The positions of the poles of those filters are shown to be particularly important.

Recently, a wavelength division multi/demultiplexing system has been viewed with keen interest because it is possible to increase the transmission capacity and system flexibility. An arrayed waveguide grating (AWG) type of Multi/demultiplexer which is one of the key components to realize such a system has been developed by using Planar Lightwave Circuits (PLCs). Newly designed optical circuits have been incorporated into the AWG to control the center wavelength and to expand the pass band width. The 3 dB pass band width is 1.4 times that of a conventional AWG. It is confirmed that the newly developed AWG has low polarization dependence, low temperature dependence and high reliability.

It is shown that two-dimensional linear phase FIR digital filters with various shapes of frequency response can be designed and realized as modular array structures free of multiplier coefficients. The design can be performed by judicious selection of two low order linear phase transfer functions to be used at each module as kernel filters. Regular interconnection of the modules in L rows and K columns conditioned with boundary coefficients 1, 0 and 1/2 results in higher order digital filters. The kernels should be chosen appropriately to, first, generate the desired shape of frequency response characteristic and, second, lend themselves to multiplierless realization. When these two requirements are satisfied, the frequency response can be refined to possess narrower transition bands by adding additional rows and columns. General properties of the frequency response of the array are investigated resulting in Theorems that serve as valuable tools towards appropriate selection of the kernels. Several design examples are given. The array structures enjoy several favorable features. Specifically, regularity and lack of multiplier coefficients makes it suitable for high-speed systolic VLSI implementation. Computational complexity of the structure is also studied.

Multipath interconnection networks can support higher bandwidth than those of nonblocking networks by passing multiple packets to the same output simultaneously and these packets are buffered in the output buffer. The delay-throughput performance of the output buffer in multipath networks is closely related to output traffic distribution, packet arrival process at each output link connected to a given output buffer. The output traffic distributions are different according to the various input traffic patterns. Focusing on nonuniform output traffic distributions, this paper develops a new, general analytic model of the output buffer in multipath networks, which enables us to investigate the delay-throughput performance of the output buffer under various input traffic patterns. This paper also introduces Multipath Crossbar network as a representative multipath network which is the base architecture of our analysis. It is shown that the output buffer performances such as packet loss probability and delay improve as nonuniformity of the output traffic distribution becomes larger.

A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75. The same margins 1.1 ns of the setup time and hold time were measured for the specifications of a setup time of 2.0 ns and a hold time of 0.5 ns.

The multiple registration schemes (MRSs) proposed here are classified into 3 cases by combining five registration schemes which are power up registration scheme (PURS), power down registration scheme (PDRS), zone based registration scheme (ZBRS), distance based registration scheme (DBRS), and implicit registration scheme (IRS) as follows: the first is MRS1 which covers PURS, PDRS, and ZBRS; the second is MRS2 which covers PURS, PDRS, and DBRS; the third is MRS3 which covers PURS, PDRS, IRS, and DBRS. The three proposed schemes are compared each other by analyzing their combined signaling traffic of paging and registration with considering various parameters of a mobile station behavior (unencumbered call duration, power up and down rate, velocity, etc.). Also, we derive allowable location areas from which the optimal location area is obtained. Numerical results show that MRS3 yields better performance than ZBRS, DBRS, MRS1, and MRS2 in most cases of a mobile station behavior, and it has an advantage of distributing the load of signaling traffic into every cell, which is important in personal communication system.

We propose an improved orthogonal frequency division multiplexing (OFDM) signal detector which uses the minimum mean-square error (MMSE) noise feedback equalization (NFE). The input bit stream is trellis-coded to form OFDM signal blocks and the maximal ratio combining (MRC) is adopted at the receiver in order to improve the performance of the detector. As a result, we obtain significantly improved detection performance compared with the conventional OFDM receivers as follows. Using the proposed MMSE-NFE in the receiver, we can obtain the performance gain of about 1.5 dB to 2 dB in symbol energy to noise power spectral density (Es/No) for Doppler frequencies of fd=20 and 100 Hz, respectively, over the receiver with the MMSE linear equalization (LE) alone at symbol error rate (SER) of about 10-3. With MRC and trellis coding, the performance gain of about 11 dB in Es/No for fd=20 and 100 Hz at SER of about 10-3 is obtained.

SCI (Scalable Coherent Interface) is pointerbased coherent directory scheme for massively parallel multiprocessors. Large message latency is one of the problems with SCI because of its linked list structure: the searching latency of messages could grow as a linear order of the number of processors. In this paper, we focus on a hierarchical architecture to propose a new schemeEST(Extending SCI-Tree), which may reduce the message traffic and also take the advantages of the topology property. Simulation results show that the EST scheme is effective in reducing message latency and communication cost when compared with other schemes.

This paper presents intelligent memory, a new memory architecture capable of providing efficient lock-free synchronization. In the intelligent memory, a sequence of operations on a shared object associated with that memory module can be processed without any intervention so that an environment for the synchronization can be provided by executing a critical section itself in that memory module. For this, we present a memory architecture for the intelligent memory having minimal instruction set and develop a progtramming model, called Critical Section Procedure (CSP), which consists of shared data structures and operations on them. Intelligent memory is intended to eliminate waste of processing time such as busy waiting in spin lock and the retry due to process contentions in existing lock-free synchronization schemes. Simulation results show that the intelligent memory provides better throughput compared with the spin lock and the existing lock-free synchronization schemes.

This paper describes a new approach to the scheduling problem that assigns tasks of a parallel program described as a task graph onto parallel machines. The approach handles interprocessor communication and heterogeneity, based on using both the theoretical results developed so far and a lookahead scheduling strategy. The experimental results on randomly generated task graphs demonstrate the effectiveness of this scheduling heuristic.

Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was discussed in previous work [1]. RPL combines advantages of both the compact size of CPL and the full voltage-swing of DPL, and gives reasonably high performance concerning both speed and power consumption. In this paper, the application and design technique of RPL on larger logic circuits and systems are reported. Parallel adders and Booth multipliers with different sizes and structures are used as examples to evaluate the functionality of the RPL gates and full adder. In addition, there is less signal skew in RPL circuits than in conventional CPL circuits when an arrangement of single-rail to dual-rail signal conversion is performed. And, RPL is found to be useful in design of high speed and high density parallel adders and multipliers.

In this paper we present an algorithm to solve an as-yet untreated knapsack problem, the Multidimensional Multiple-choice Knapsack Problem (MMKP). Since our specific application occurs in the real-time domain, a solution for the MMKP with a small upper bound on the runtime is desirable. Thus, the Lagrange multiplier method is chosen, and a heuristic with a worst-case runtime behavior better than O(n2m) is developed, n being the number of elements and m the number of dimensions. Extensive testing against an exact algorithm based on partial enumeration is used to establish the accuracy and efficiency of the heuristic.

The parasitic bipolar effect in a 200-V-class thin-film SOI power MOSFET fabricated using the silicon wafer direct bonding wafer was investigated by electrical measurement, two-dimensional process simulation, emission microscopy, and 2-dimensional thermal analysis. It degraded the breakdown voltage of the thin-film SOI power MOSFET and was caused by the increase in the sheet resistance of the body contact region. Photo emission analysis indicated that excess holes recombined in the n+-source region.

In this paper we describe the implementation of complex architectures using a general design approach for two-phase asynchronous systems. This fundamental approach, called Event Controlled Systems, can be used to widely extend the utility of two phase systems. We describe solutions that we have developed that dramatically improve the performance of static and dynamic-logic asynchronous pipelines, and briefly describe a complex microprocessor designed using ECS.