This paper presents a divide-by-9 injection-locked frequency divider (ILFD). It can lock onto about 6-GHz input with a locking range of 3.23GHz (58%). The basic concept of the ILFD is based on employing self-gated multiple inputs into the multiple-stage ring oscillator. A wide lock range is also realized by adapting harmonic-control circuits, which can boost specific harmonics generated by mixing. The ILFD was fabricated using a 55-nm deeply depleted channel (DDC) CMOS process. It occupies an area of 0.0210mm2, and consumes a power of 14.4mW.

A monolithic frequency synthesizer with wide tuning range, low phase noise and spurs was realized in 0.13,$mu$m CMOS technology. It consists of an analog PLL, a harmonic-rejection mixer and injection-locked frequency doublers to cover the whole 6--18,GHz frequency range. To achieve a low phase noise performance, a sub-sampling PLL with non-dividers was employed. The synthesizer can achieve phase noise $-$113.7,dBc/Hz@100,kHz in the best case and the reference spur is below $-$60,dBc. The core of the synthesizer consumes about 110,mA*1.2,V.

Parametric resonance based solutions for sub-gigahertz radio frequency transceiver with 0.3V supply voltage are proposed in this paper. As an implementation example, a 0.3V 720µW variation-tolerant injection-locked frequency multiplier is developed in 90nm CMOS. It features a parametric resonance based multi-phase synthesis scheme, thereby achieving the lowest supply voltage with -110dBc@ 600kHz phase noise and 873MHz-1.008GHz locking range in state-of-the-art frequency synthesizers.

This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.

This paper derives a maximum lock range of an injection locked ring oscillator in a direct injection method and presents an injection locked charge-pump phase-locked loop (CPPLL) with a replica of a ring oscillator. The proposed injection-locked PLL separates the injection-locked VCO from the continuous phase-tracking loop of the PLL such that can provide stable lock-state maintenance and tolerance to temperature and supply voltage variation. The measurement results show that the proposed injection-locked PLL can be tolerable to voltage variation of 11.2% in supply voltage of 1.2V. In-band noises of the injection-locked oscillator at offset frequencies of 10kHz and 100kHz are -108.2dBc/Hz and -114.6dBc/Hz, respectively.

A novel divide-by-3 injection-locked frequency divider (ILFD) is proposed. The ILFD circuit is realized with a cross-coupled n-core MOS LC-tank oscillator embedded with a push-push signal generator and two injection MOSFETs for coupling the injection signal into the resonator. The ILFD uses the linear mixer to extend the locking range and has been implemented in a standard 0.18 µm CMOS process. The core power consumption of the ILFD core is 3.12 mW. The divider's free-running frequency is tunable from 4.26 GHz to 4.9 GHz by tuning the varactor's control bias, and at the incident power of 0 dBm the locking range of the ILFD used as a divide-by-3 divider is 1.5 GHz, from 12.5 GHz to 14.0 GHz.

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98 dBc/Hz. The locking range of the PLL is from 22.6 GHz to 23.3 GHz and the reference spur level is -69 dBm that is 54 dB bellow the carrier. The power consumption is 9.2 mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

A dual-band divide-by-2 quadrature injection-locked frequency divider (QILFD) is proposed to achieve high-speed, low power, wide-locking range, and accurate quadrature output phases. The QILFD consists of two dual-resonance differential voltage controlled oscillators and four coupling NMOS injectors in a ring configuration. The injectors are used as coupling devices of two differential ILFDs and are also used as common source amplifiers. The proposed QILFD has been implemented with the TSMC 90 nm CMOS technology and the core power consumption is 2.31 mW at the dc drain-source bias of 0.5 V. At the input power of 0 dBm, the low-band and high-band divide-by-2 operation ranges are respectively from 7.0 GHz to 10.1 GHz and 19.8 GHz to 24.6 GHz.

This paper presents a real integration of a 5.8-GHz injection-locked quadrature local oscillator that includes two LC-tuned injection-locked frequency dividers (ILFDs) and a wide-tuning stacked-transformer feedback voltage-controlled oscillator (VCO) operated in double frequency. A symmetric differential stacked-transformer with a high coupling factor and a high quality factor is used as a feedback component for the wide-tuning VCO design. The wide tuning range, which is greater than three times the desired bandwidth, is achieved by selecting a greater tuning capacitance ratio available from high-voltage N-type accumulation-mode MOS varactors and a smaller self-inductance stacked-transformer. Since the quality factors of the LC-resonator components can sustain at a high enough level, the wide-tuning VCO does not suffer from the phase noise degradation too much. In addition, the tuning range of the local oscillator is extended simultaneously by utilizing switched capacitor arrays (SCAs) in the ILFDs. The circuit is implemented by TSMC's 0.18-µm RF CMOS technology. At a 1-V power supply, the whole integrated circuit dissipates 6.72 mW (4.05 mW for the VCO and 2.67 mW for the two ILFDs). The total tuning range frequency is about 500 MHz (from 5.54 GHz to 6.04 GHz) when the tuning voltage Vtune ranges from 0 V to 1.8 V. At around the output frequency of 5.77 GHz (at Vtune = 0.5 V), the measured phase noise of this local oscillator is -119.4 dBc/Hz at a 1-MHz offset frequency. This work satisfies the specification requirement for IEEE 802.11a UNII-3 band application. The corresponding figure-of-merit (FOM) calculated is 186.3 dB.

This paper proposes a wide-locking range divide-by-3 injection-locked frequency divider (ILFD) fabricated in the 90 nm 1P9M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled nMOSFETs. The ILFD is formed with two linear mixers which share the same dc current so that a low power ILFD can be designed. At the supply voltage of 0.7 V, the free-running frequency is from 10.18 to 11.56 GHz, the current and power consumption of the divider without buffers are 2.8 mA and 1.96 mW, respectively. At the incident power of 0 dBm, the total operational locking range is 4.94 GHz, from the incident frequency 29.96 to 34.9 GHz.

This letter presents a new quadrature voltage-controlled oscillator (QVCO) consisting of two n-core Colpitts voltage-controlled oscillators (VCOs) with a tail inductor. The VCOs are used as a single-ended injected injection-locked frequency divider (ILFD). The output of the tail inductor in one ILFD is injected into the injection node in the other ILFD and vice versa. The proposed QVCO has been implemented in the 0.18 µm CMOS technology. At the supply voltage of 1.0 V, the power consumption is 1.8 mW. The free-running frequency is tunable from 4.68 GHz to 5.03 GHz as the tuning voltage is varied from 0.0 V to 1.8 V. The measured phase noise is -113.58 dBc/Hz at the 1 MHz frequency offset from the oscillation frequency of 5.03 GHz and the figure of merit (FOM) of the QVCO is -185.06 dBc/Hz.

A dual band 0.18 µm CMOS LC-tank injection locked frequency divider (ILFD) is proposed. The ILFD circuit is realized with a cross-coupled pMOS LC-tank oscillator with an inductor switch for frequency band selection. The self-oscillating VCO is injection-locked by nth-harmonic input to obtain the division factor of n. The division ratio of 1, 2, and 3 has been found for the proposed ILFD. Measurement results show that at the supply voltage of 1.1 V, the free-running frequency is from 2.28(3.09) GHz to 2.78(3.72) GHz for the low- (high-) frequency band. The power consumption of the ILFD core is 3.7 mW (6.2 mW) at low (high) band. The total area including the output buffer and the pads is 0.8410.764 mm2.

This paper proposes a wide-locking range divide-by-3 frequency divider employing 3D helical inductors fabricated in the 0.18-µm 1P6M CMOS technology. The divider consists of an nMOS cross-coupled LC oscillator and two injection MOSFETs in series with the cross-coupled NMOSFETs, and the LC resonator is composed of two 3D helical inductors and varactors. The aim of using 3D inductor is to reduce chip size. At the supply voltage of 1.2 V, the divider free-running frequency is tunable from 2.1 GHz to 2.6 GHz, and at the incident power of 0 dBm the locking range is about 2.11 GHz (29.16%), from the incident frequency 5.99 GHz to 8.1 GHz. The core power consumption is 4.56 mW. The die area is 0.6640.831 mm2.

This paper presents a quadrature injection locked frequency divider (ILFD) employing tunable active inductors (TAIs), which are used is to extend the locking range and to reduce die area. The CMOS ILFD is based on a new quadrature voltage-controlled oscillator (VCO) with cross-coupled switching pairs and TAI-C tanks, and was fabricated in the 0.18-µm 1P6M CMOS technology. The divide-by-2 LC-tank ILFD is performed by adding injection MOSFETs between the differential outputs of the VCO. Measurement results show that at the supply voltage of 1.8 V, the divider free-running frequency is tunable from 1.34 GHz to 3.07 GHz, and at the incident power of 0 dBm the locking range is about 6 GHz (137%), from the incident frequency 1.37 GHz to 7.38 GHz. The core power consumption is 22.8 mW. The die area is 0.630.55 mm2.

A radio-on-dense-wavelength-division-multiplexing (DWDM) transport system based on injection-locked Fabry-Perot laser diodes (FP LDs) with four microwave carriers and large effective area fiber (LEAF) transmission was proposed and demonstrated. Good performance of bit error rate (BER) and intermodulation distortion to carrier ratio (IMD/C) over a-50 km of LEAF was obtained. Signal quality meets the demands of personal handy system (PHS)/vehicle information and communication system (VICS)/electronic toll collection (ETC)/satellite broadcasting (SB).

An injection-locked clock recovery circuit (CRC) with quadrature outputs based on multiplexed oscillator is presented. The CRC can operate at a half-rate speed to provide an adequate locking range with reasonable jitter and power consumption because both clock edges sample the data waveforms. Implemented by 0.18-µm CMOS technique, experimental results demonstrate that it can achieve the phase noise of the recovered clock about -121.55 dBc/Hz at 100-kHz offset and -129.58 dBc/Hz at 1-MMz offset with 25 MHz lock range, while operating at the input data rate of 1.55 Gb/s.

A new scheme for reducing optical beat interference noise in a reflective semiconductor optical amplifier based wavelength division multiplexed/subcarrier multiplexing -- passive optical network is proposed. This method uses an Fabry Perot laser locked by modulated lights from optical network units in a central office. As an experimental verification, it is reported that carrier to noise ratio is enhanced by 10 dB and power penalty is improved by 16 dB.

This paper discusses direct optical injection locking of a millimeter-wave oscillator using an InP/InGaAs heterojunction phototransistor (HPT) and its applications. Previously reported optically injection-locked oscillators (OILOs) are reviewed first. In particular, the features of a direct OILO (DOILO), where synchronization can be achieved by illuminating the active oscillator device itself, are discussed in comparison with the indirect OILO. DOILOs with excellent characteristics require high-performance transistors having both a high maximum oscillation frequency and fast photoresponse. We have developed high-performance opto-microwave-compatible InP/InGaAs HPTs whose layer and fabrication process are fully compatible with ultrahigh-speed heterojunction bipolar transistors. The paper discusses the photocoupling structure, and it is shown that the back-illuminated structure with the aid of InP subcollector enables one to achieve a 100-GHz-class DOILO. The configuration and performance of the 100-GHz-class DOILO are then presented; in particular, injection locking from optical signals with a modulation or beat frequency of around the fundamental (96 GHz) or second harmonic (192 GHz) is successfully demonstrated. To our knowledge, 96 GHz is the highest optically injection-locked frequency and 192 GHz is the highest inputmodulation frequency reported for OILOs. The HPT oscillator IC promises compact, low-power-consumption remote local oscillators for 100-GHz-class wireless systems and 100-Gbit/s-class optoelectronic clock recovery circuits. In addition, when the HPT oscillator is used as a modulator, we can attain cost-effective millimeter-wave systems compatible with conventional optical fiber networks transmitting digitally modulated baseband signals.

In this paper, the analysis, design and experimental results of active array applicator are presented. The injection-locking technique is used to alter the magnitude of the microwave sources so that the steering of near fields can be achieved. This technique can be applied for microwave hyperthermia cancer treatment to provide the large uniform temperature distribution. The complexity of the system can be reduced by using this technique. The study shows that the temperature distribution can be controlled by varying the modulation index, modulating frequency and initial phase of modulating signal. The temperature distribution is also affected by applicator configuration, spacing between applicators, and heating time. The Spectral Domain approach is used to analyze the near field and then the near field data are used to find the temperature distribution by using the Finite Difference method. The study is carried out at frequency of 2,450 MHz. This design is useful for implementation of the low cost steerable applicator.

Subharmonically Injection-locked oscillators (ILO's) with very wide injection-locking ability are presented. Two types of ILO MMIC's with this ability are proposed. The oscillation frequency tuning function of the ILO MMIC is very useful for expansion of the injection locking range at higher subharmonics. One consists of a shunt varactor diode inserted into the oscillation loop, and the other incorporates a vector-combining configuration with in-phase divider and 90 degree hybrid. Using three-dimensional MMIC's technology which can offer miniature and high-density passive circuits, the vector-combining type ILO is formed in a very compact area of 1. 7 mm2. Fabricated 20 GHz-band ILO achieves a wide tuning ranges of 870 MHz, resulting in a very wide locking range for higher subharmonics. The wide frequency tuning ability also reduces phase noise, shortens a locking time and compensates the center frequency deviation against temperature, as well as increasing locking range. The measured results show that the ILO configuration is extremely suitable for realizing simple, fully monolithic and low phase noise millimeter-wave frequency synthesizers.