This paper provides an architectural study of optical ring trunk-transmission networks using either Time Division Multiplexing (TDM) or Wavelength Division Multiplexing (WDM). A timeslot arrangement algorithm for distributed controlled TDM rings is proposed that minimizes the number of slots (wavelengths) required in bi-directional ring networks. This algorithm is applied in a straightforward manner to wavelength arrangement in WDM ring networks. The technique, characterized by timeslot (or wavelength) conversion, realizes common add/drop procedures in all Add/Drop Multiplexers (ADMs) when they are connected logically in a mesh topology. A self-healing algorithm is also proposed for network restoration. It offers good performance in terms of protection line-capacity, restoration delay, and survivability against multiple failures.

Various reconfiguration schemes against faults of mesh-connected processor arrays have been proposed. As one of them, the mesh-connected processor arrays model based on single-track switches was proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. Furthermore, the 2 track switch model [2] and the multiple track switch model [3] were proposed to enhance yields and reliabilities of arrays. However, in these models, Simplicity of the routing hardware is somewhat lost because multiple tracks are used for each row and column. In this paper, we present a builtin self-reconstruction approach for mesh-connected processor arrays which are partitioned into sub-arrays each using single-track switches. Spare PEs which are located on the boundaries of the sub-arrays compensate faulty PEs in these sub-arrays. First, we formulate a reconfigulation algorithm for partitioned mesh-arrays using a Hopfield-type neural network, and then its performance for reconfigulation in terms of survival rates and reliabilities of arrays and processing time are investigated by computer simulations. From the results, we can see that high reliabilites are achieved while processing time is a little and hardware overhead (links and switches) required for reconstruction is as same as that for the track switch model. Next, we present a hardware implementation of the neural algorithm so that a built-in self-reconfigurable scheme may be realized.

A self-organizing neural network model of spatio-temporal visual receptive fields is proposed. It consists of a one-layer linear learning network with multiple temporal input channels, and each temporal channel has different impulse response. Every weight of the learning network is modified according to a Hebb-type learning algorithm proposed by Sanger. It is shown by simulation studies that various types of spatio-temporal receptive fields are self-organized by the network with random noise inputs. Some of them have similar response characteristics to X- and Y-type cells found in mammalian retina. The properties of receptive fields obtained by the network are analyzed theoretically. It is shown that only circularly symmetric receptive fields change their spatio-temporal characteristics depending on the bias of inputs. In particular, when the inputs are non-zero mean, the temporal properties of center-surround type receptive fields become heterogeneous and alter depending on the positions in the receptive fields.

A data-flow program net is a graph representation of data-flow programs consisting of three types of nodes, AND-node, OR-node and SWITCH-node, which represent arithmetic/logical, data merge and context switch operations respectively. Token self-cleanness is an important property of a data-flow program and is such that if date-flow programs satisfy the property then a date-flow computer can efficiently withdraw copies from given programs during executions. In this paper, we classify program nets into SWITCH-less, OR-less and general nets, and analyse structures of data-flow program nets to propose verification methods of token self-cleanness by investigating token numbers appearing on the edges. As a result, a necessary and sufficient condition is proposed for SWITCH-less data-flow program nets and sufficient conditions are given for OR-less and general data-flow program nets.

Digital halftoning is a well-known technique in image processing to convert an image having several bits for brightness levels into a binary image consisting only of black and white dots. A great number of algorithms have been presented for this problem, some of which have only been evaluated just by comparison with human eyes. In this paper we formulate the digital halftoning problem as a combinatiorial problem which allows an exact solution with graph-theoretic tools. For this, we consider a d-dimensional grid of n := Nd pixels (d 1). For each pixel, we define a so-called k-neighborhood, k {0,...N - 1}, which is the set of at most (2k + 1)d pixels that can be reached from the current pixel in a distance of k. Now, in order to solve the digital halftoning problem, we are going to minimize the sum of distances of all k-neighborhoods between the original picture and the halftoned one. We show that the problem can be solved in linear time in the one-dimensional case while it looks hopeless to have a polynomial-time algorithm in higher dimension including the usual two-dimensional case. We present an exact algorithm for the one-dimensional case which runs in O(n) time if k is regarded to be a constant. For two-dimensional case we present fast approximation techniques based on space filling curves. An experimental comparison of several implementations of approximate algorithms proves that our algorithms are of practical interest.

Using fundamental device and circuits, we have realized three functions required for synaptic connections in self-organizing neural networks: long term memory of synaptic weights, fixed total amount of synaptic weights in a neuron, and lateral inhibition. The first two functions have been condensed into an optical adaptive device and circuits with floating gates. Lateral inhibition has been realized by a winner-take-all circuit and a following lateral excitatory connection circuit. We have fabricated these devices and circuits using CMOS technology and confirmed the three functions. In addition, topological mapping, which is essential for feature extraction, has been formed in a primitive network constructed with the fundamental device and circuits.

We present a new method for the self-tuning control (STC) of nonminimum phase continuous-time systems based on the pole-zero placement. The long division method is used to decompose a polynomial into a stable and unstable polynomials. It is also shown that the effect of unstable zeros on the magnitude of the desired output can be cancelled. Finally, the results of computer simulation are presented to illustrate the effectiveness of the proposed method.

We have developed the Epi-Base SATURN process as a silicon bipolar process technology which can be applied to optical transmission LSIs. This process technology, to which low temperature selective epitaxial growth technology is applied, is based on the SATURN process. By performing selective epitaxial growth for base formation in 2 steps, transistors with a 40GHz maximum cut-off frequency have been fabricated. In circuit simulation based on SPICE parameters of transistors, the target performance required for 2.4 Gbit/s optical interface LSIs has been achieved.

The Voronoi diagram is the most fundamental and useful concept in computational geometry. To understand impacts of non-Euclidean geometry on computational geometry, this paper investigates the Voronoi diagram in hyperbolic space. We first present characterizations of this diagram by means of the Enclidean Voronoi diagram, and based on them propose efficient algorithms to construct it. Some applications are also mentioned.

An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a Vcc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.

Throughout the paper, the proper operating of the self-routing principle in 2-D shuffle multistage interconnection networks (MINs) is analysed. (The notation 1-D MIN and 2-D MIN is applied for a MIN which interconnects 1-D and 2-D data, respectively.) Two different methods for self-routing in 2-D shuffle MINs are presented: (1) The application of self-routing in 1-D MINs by a switch-pattern preserving transformation of 1-D shuffle stages into 2-D shuffle stages (and vice versa) and (2) the general concept of self-routing in 2-D shuffle MINs based on self-routing with regard to each coordinate which is the original contribution of the paper. Several examples are provided which make the various problems transparent.

A simplified distribution base resistance model (SDM) is proposed to identify each component of the base resistance and determine the dominant. This model divides the parasitic base resistance into one straight path and two surrounding paths. It is clarified that the link base resistance is dominant in a short emitter and the surrounding polysilicon base electrode resistance is dominant in a long emitter. In the SDM, the distance of the link base is reduced to half; with metal silicide as the extrinsic base electrode, the base resistance will be reduced to 75%.

The degradation of I-V characteristics under constant emitter-base reverse voltage stress in advanced self-aligned bipolar transistors was analyzed. Experimental analyses have been taken the stress field effect into account when predicting hot-carrier degradation. These analyses showed that base current starts to increase when the reverse voltage stress is about 3 V. The dependence of the base current change on reverse voltages of more than 3 V was also investigated experimentally, and equations expressing hot-carrier degradation in terms of the exponential dependence of excess base current on both reverse stress voltage and stress-enhancing voltage related to emitter-base breakdown voltage were derived.

This paper proposes a distributed built-in self-test (BIST) technique and its test design platform for VLSIs. This BIST has lower hardware overhead pattern generators, compressors and controller. The platform cuts down on the number of complicated operations needed for the BIST insertion and evaluation, so the BIST implementation turn-around-time (TAT) is dramatically reduced. Experimental results for the 110 k-gate arithmetic execution blocks of an image-processing LSI show that using this BIST structure and platform enables the entire BIST implementation within five days. The implemented BIST has a 1% hardware overhead and 96% fault coverage. This platform will significantly reduce testing costs for time-to-market and mass-produced LSIs.

In order to provide a fuzzy system with learning function, numerous studies are being carried out to combine fuzzy systems and neural networks. The self-tuning methods using the descent method have been proposed. The constructive and the destructive methods are more powerful than other methods using neural networks (or descent method). On the other hand the destructive method is superior in the number of rules and inference error and inferior in learning speed to the constructive method. In this paper, we propose a new learning method combining the constructive and the destructive methods. The method is superior in the number of rules, inference error and learning speed to the destructive method. However, it is inferior in learning speed to the constructive method. Therefore, in order to improve learning speed of the proposed method, simplified learning methods are proposed. Some numerical examples are given to show the validity of the proposed methods.

In this paper, a new optimum input encoding algorithm with m-out-of-2m code which is called Half-Hot Code is presented. By applying Half-Hot Code to the input encoding in PLA-based digital system, the logic functions of the system turn out to be unate functions, thus, the number of bit-lines of PLA may be reduced. The proposed method further reduces the number of product-lines of PLA optimally. In this code assignment procedure, computed Boolean subspaces satisfying suggeset two conditions are assigned to each partitioned subset of digital input variables which are obtained by disjoint minimization or other techniques. As an experiment to evaluate the method, the state assignment for finite state machines of two-lavel implementation is considered. Specifically, the proposed Half-Hot Code assignment is compared with arbitrary Half-Hot Code assignment. The results show that the optimum encoding is superior to an arbitrary assignment up to about 24% in the number of product-lines of PLA.

Recent high-speed bipolar technologies based on SICOS (Sidewall Base Contact Structure) transistors are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. As the characteristics of the upward operated SICOS transistors are close to those of downward transistors, they can easily be applied in memory cells which have near-perfect soft-error-immunity. Newly developed process technologies for making shallow base and emitter junctions to improve circuit performance are also reviewed. Finally, complementary bipolar technology for low-power and high-speed circuits using pnp transistors, and a quasi-drift base transistor structure suitable for below 0.1 µm emitters are discussed.

High speed GaAs ICs (Integrated Circutis) using FETs (Field Effect Transistors) are reported. As the fabricating techniques, ion implantation processes for both 0.5 µm and 0.2 µm gate FETs using W/Al refractory metal and 0.2 µm recessed gate process with MBE grown epitaxial wafers are shown. These fabrication processes are selected depending on the circuit speed and the integration level. The outline of the circuit design and the examples of ICs, which are developed for 10 Gb/s optical communication systems, are also shown with the obtained characteristics.

Transition coverage has been proposed as a measure of two-pattern test capabilities of TPG circuits for use in BIST. This paper investigates experimentally the relationships between transition coverages and actual stuck-open fault coverages in order to reveal what kind of circuits are appropriate for two-pattern testing. Fault simulation was performed using conventional (n-stage) LFSR, 2n-stage LFSR, and one-dimensional cellular automata (CAs) as TPG circuits and such sample circuits as balanced NAND tree and some ISCAS '85 benchmark circuits as CUTs. It was found that CAs which are designed so as to apply exhaustive transitions to any 3-dimensional subspaces can detect high rate of stuck-open faults. Influence of hazards of decreasing the fault coverage is also mentioned.

This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.