The disturbance-rejection problem is to find a feedback control law for linear control systems such that the influence of disturbances is completely rejected from the output. In 1970 Wonham and Morse first studied this problem in the framework of the so-called geometric approach. On the other hand, in 1985 Ghosh studied parameter insensitive disturbance-rejection problems with state feedback and with dynamic compensator. In this paper we study the parameter insensitive disturbance-rejection problem with static incomplete-state feedback for linear multivariable systems in the framework of the geometric approach from the mathematical point of view. Necessary conditions and/or sufficient conditions for this problem to be solvable are presented. Finally an illustrative example is presented.

In this paper, a new optimum input encoding algorithm with m-out-of-2m code which is called Half-Hot Code is presented. By applying Half-Hot Code to the input encoding in PLA-based digital system, the logic functions of the system turn out to be unate functions, thus, the number of bit-lines of PLA may be reduced. The proposed method further reduces the number of product-lines of PLA optimally. In this code assignment procedure, computed Boolean subspaces satisfying suggeset two conditions are assigned to each partitioned subset of digital input variables which are obtained by disjoint minimization or other techniques. As an experiment to evaluate the method, the state assignment for finite state machines of two-lavel implementation is considered. Specifically, the proposed Half-Hot Code assignment is compared with arbitrary Half-Hot Code assignment. The results show that the optimum encoding is superior to an arbitrary assignment up to about 24% in the number of product-lines of PLA.

This paper describes an MOS charge-mode version of a T-Model neural-based PCM encoder. The neural-based PCM encoding networks are designed, simulated and implemented using MOS charge-mode circuits. Simulation results are given for both the T-Model and the Hopfield model CMOS charge-mode PCM encoders, and demonstrate the T-Model neural-based one performs the PCM encoding perfectly, while the Hopfield one fails to.

In this paper, two models are proposed for the simulation of MPEG video sources in ATM networks. The projected autoregressive (PAR) model is based on the autoregressive (AR) model compensated by a projection function. The projection function is capable of adjusting the histogram generated by the AR model so that it better fits the histogram obtained from real data. The state transition (ST) model is developed on die basis of recording the variation of frame size in a video sequence. Each state denotes the size of a frame and the number of state depends on the degree of correlation between frames. Our results show that the histogram generated by the ST model is almost identical with that of the real data and the PAR model performs better in capturing the property of autocorrelation of real data. When compared with other models, both of the two models demonstrate an excellent property of fitting the complex histogram curve, which was not achieved by the AR model, and preserving the correlation characteristics. A heuristic search algorithm is also proposed to make our modelling processes more efficient.

In this paper, we describe a worst-case design optimization approach for statistical design of integrated circuits with a circuit performance model scheme. After formulating worst-case optimization to an unconstrained multi-objective function minimization problem, a new objective function is proposed to find an optimal point. Then, based on an interpolation model scheme of approximating circuit performance, realistic worst-case analysis can be easily done by Monte Carlo based method without increasing much the computational load. The effectiveness of the presented approach is demonstrated by a standard test function and a practical circuit design example.

An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.

A technique for pulse code modulation (PCM) encoding using a T-Model neural network is described. Performance evaluation on both the T-Model and the Hopfield model neural-based PCM encoders is carried out with PSpice simulations. The PSpice simulations also show that the T-Model neural-based PCM encoder computes to a global minimum much more effectively and more quickly than the Hopfield one.

We present distributed load balancing mechanisms implemented on multiprocessor systems for real time video encoding, which dynamically equalize load amounts among PE's to cope with extensive computing requirements. The loosely coupled multiprocessor system, e.g. a torus connected one, is treated as the objective system. Two decentralized controlled load balancicg algorithms are proposed, and mathematical analyses are provided to obtain some insights of our decentralized controlled mechanisms. We also prove the proposed algorithms are steady and effective theoretically and experimentally.

It is an important problem whether or not we can reject the disturbances from distributed parameter circuit. In order to analyze this problem structurally, it is necessary to investigate the basic equation of distributed parameter circuit in the framework of state space. Since the basic equation has two parameters for time and space, the state value belongs to an infinite-dimensional space. In this paper, the disturbance-rejection problems with incomplete state feedback and/or incomplete state feedback and feedforward for infinite-dimensional systems are studied in the framework of geometric approach. And under certain assumptions, necessary and/or sufficient conditions for these problems to be solvable are proved.

The theoretical modelling bandgap narrowing and percentage of ionized impurity atoms for uncompensated uniformly doped silicon containing conventional impurities (B, P, As, Sb) under thermodynamic-equilibrium conditions is presented. As distinct from existing approaches, this modelling is valid for impurity concentrations up to electrically-active-impurity-concentration limits and for the temperature range from 40 K up to 400 K. A relevant and efficient calculation software is proposed. The results of the calculations are compared with the results extracted by many authors from measurement data. A good agreement between these results is noted and possible reasons of some discrepancies are pointed out. The present modelling and software can be used for investigation of BJT charge-neutral regions as well as diffused or implanted resistors.

This paper describes a monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor Vbe matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within 0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of 59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0 4.2-mm2 chip integrating 36K elements, which consumes 4.0 W using a 1.0-µm-rule, 25-GHz ft, double-polysilicon self-aligned bipolar technology.

Subjective quality tests have proven that embedded adaptive differential PCM (ADPCM), known to tolerate information loss through bit dropping, does not maintain sufficient speech quality when directly applied to asynchronous transfer mode (ATM) due to the fixed-length cell transmission scheme unique to ATM. We propose a coding and transmission scheme which enhances the performance by adjusting the embedded ADPCM coding rate according to input speech characteristics, thereby taking advantage of the ATM environment, where the transmission of variable rate sources is feasible. By varying the number of code bits of an embedded ADPCM coder from 6bits per sample, or 48kbps, for blocks of speech with a high prediction gain, to 2bits, or 16kbps, for silent blocks, a good compromise between coding bit rate and speech quality with gradual degradation due to information loss is achieved. The results of subjective evaluation tests showed the speech quality of the proposed scheme to be over 3.5 mean opinion score (MOS) on a scale of 1 to 5 at a cell loss rate of 10%. A prototype of the codec and the ATM cell assembly/disassembly functions were also fabricated using 3 conventional digital signal processors (DSPs) for real-time conversation tests.

The transmission of HDTV signals on digital networks requires adoption of sophisticated compression techniques to limit the bit-rate requirements and to provide a high-quality and reliable services to customers. This paper describes system design and transmission characteristics of an adaptive subband DCT codec that can encode original 1.2Gb/s HDTV signals at 156Mb/s. The performance of the codec was evaluated using motion picture signals. The characteristics obtained with the codec was found to maintain good picture quality.

This paper presents a design of a new multiple-valued matching VLSI processor for high-speed reasoning. It is useful in the application for real-time rule-based systems with large knowledge bases which are programmable. In order to realize high-speed reasoning, the matching VLSI processor can perform the fully parallel pattern matching between an input data and rules. On the based of direct multiple-valued encoding of each attribute in an input data and rules, pattern matching can be described by using only a programmable delta literal. Moreover, the programmable delta literal circuit can be easily implemented using two kinds of floating-gate MOS devices whose threshold voltages are controllable. In fact, it is demonstrated that four kinds of threshold voltages in a practical floating-gate MOS device can be easily programmable by appropriately controlling the gate, the drain and the source voltage. Finally, the inference time of the quaternary matching VLSI processor with 256 rules and conflict resolution circuits is estimated at about 360 (ns), and the chip area is reduced to about 30 percent, in comparison with the equivalent binary implementation.

We consider an asymptotically sparsely encoded associative memory. Patterns are encoded by n-dimensional vectors of 1 and 1 generated randomly by a sequence of biased Bernoulli trials and stored in the network according to Hebbian rule. Using a heuristic argument we derive the following capacities:c(n)ne/4k log n'C(n)ne/4k(1e)log n'where, 0e1 controls the degree of sparsity of the encoding scheme and k is a constant. Here c(n) is the capacity of the network such that any stored pattern is a fixed point with high probability, whereas C(n) is the capacity of the network such that all stored patterns are fixed points with high probability. The main contribution of this technical paper is a theoretical verification of the above results using the Poisson limit theorems of exchangeable events.

An optical On-Off Keyed (OOK) pulse is often stretched in dispersive channels, thus producing intersymbol interference (ISI) and degrading the performance. In this paper, error probability is presented for a convolutionally encoded optical OOK channels with ISI. Both ISI-matched and ISI-mismatched decoders are taken into account in the error probability analysis. The encoded optical OOK signal is received by Avalanche Photo Diode (APD) and the number of APD output photo-electrons is counted for soft decision Viterbi decoding. Error probability is derived for a 3-bit and an ideal soft decision schemes in ISI-mismatched decoder and for an ideal soft decision scheme in ISI-matched decoder. Numerical results demonstrate the effects of mismatching or 3-bit soft decision scheme. Some computer simulations are carried out to confirm the validity of the analysis.

This paper presents four-valued dynamic encoder and decoder circuits for CMOS multivalued logic systems. The circuits presented here are implemented using a new logical voltage generator and a simplified pass transistor circuit. The logical voltage generator operates with higher speed than the conventional circuit. And the simplified pass transistor circuit contributes to reducing the number of transistors. these circuits have several advantages such as a simple configuration, high speed and low power dissipation. The circuit simulation for the proposed circuits has been performed using SPICE2 program.

Voyager Neptune radio science data were collected using three antennas on Earth on August 25, 1989. A parabolic antenna at Canberra, Australia, of 70 meter diameter received 2.3GHz and 8.4GHz carriers. The 64 meter parabolic antennas at Parkes. Australia and Usuda, Japan, received only the 8.4GHz and only the 2.3GHz carriers, respectively. It is necessary to reduce the frequency variation in the received signal carrier to extract accurate information on physically interesting objects such as Neptune's atmosphere, ionosphere, or the rings. After the frequency stabilization process, the frequency drift was reduced from 180Hz down to a maximum of 5Hz, making it possible to reduce the data bandwidth and, consequently, the data volume, by a factor of 30. The uncertainty of the signal frequency estimates were also reduced from 5 down to 510-3Hz/sec above the atmosphere, from 5 down to 0.5Hz/sec in the atmosphere, and from 50 down to 3Hz/sec at the beginning and the end of the atmospheric occultation. Much of the remaining uncertainty is due to scintillations in Neptune's atmosphere and cannot be reduced further. The estimates are thus meaningfully accurate and suitable for scientific analysis and coherent arraying of data from different antennas. Two results based on these estimates are shown: a preliminary temperature-pressure (T-p) profile of Neptune's atmosphere down to a pressure level of 2 bar computed using the Usuda 2.3GHz data, and a multipath phenomenon in the atmosphere seen in Canberra 8.4GHz data. Our T-p profile shows good agreement with the results presented by Lindal et al. within 1K below 100mbar pressure level, even though our result is based on an independent data set and processing. A comparison of the multipath phenomena at Neptune with that at Uranus implies that it was created by a cloud layer with a smaller scale height than the atmosphere above and below it. The processing methods described were developed in part with the interest to coherently array Canberra, Parkes and Usuda data. In this sense, while this paper does not extend any science results, the observations and results are derived independently from other published results, and in the case of Usuda, are completely new.