A primary-side regulation AC--DC constant voltage control chip is designed, which employs a novel cable compensation technique to improve the precision of the output voltage and pursue a wider load range for regulation. In the proposed controller, constant voltage (CV) is achieved by OSC charging current and current-limiting point adjustment. Meantime, according to different cable lengths, the sampled voltage is regulated by injecting current to pull-down resistance of the system to obtain an accurate output voltage. The proposed chip is implemented in TSMC 0.35,$mu $m 5,V/40,V BCD process, and a 12,V/1,A circuit prototype has been built to verify the proposed control method. Experimental results show that the maximum cable compensation current reaches 43,$mu $A, and the precision of the output voltage is within $pm$ 3% in a wide range of output current from 0 to 1,A.

TTFF (Time-To-First-Fix) is an important indicator of GPS receiver performance, and must be reduced as much as possible. Bit synchronization is the pre-condition of positioning, which affects TTFF. The frequency error leads to power loss, which makes it difficult to find the bit edge. The conventional bit synchronization methods only work well when there is no or very small frequency error. The bit synchronization process is generally carried out after the pull-in stage, where the carrier loop is already stable. In this paper, a new bit synchronization method based on frequency compensation is proposed. Through compensating the frequency error, the new method reduces the signal power loss caused by the accumulation of coherent integration. The performances of the new method in different frequency error scenarios are compared. The parameters in the proposed method are analyzed and optimized to reduce the computational complexity. Simulation results show that the new method has good performance when the frequency error is less than 25Hz. Test results show that the new method can tolerate dynamic frequency errors, and it is possible to move the bit synchronization to the pull-in process to reduce the TTFF.

Negative feedback technique employing high DC gain operational amplifier (op-amp) is one of the most important techniques in analog circuit design. However, high DC gain op-amp is difficult to realize in scaled technology due to a decrease of intrinsic gain. In this paper, high DC gain op-amp using common-gate topology with high power efficiency is proposed. To achieve high DC gain, large output impedance is required but input transistors' drain conductance decreases output impedance of conventional topology such as folded cascode topology with complementary input. This is because bias current of the output side transistors is not separated from the bias current of the input transistors. On the other hand, proposed circuit can suppress a degradation of output impedance by inserting common-gate topology between input and output side. This architecture separates bias current of the input transistors from that of the output side, and hence the effect of the drain conductance of input transistors is reduced. As the result, proposed circuit can increase DC gain about 10,dB compared with the folded cascode topology with complementary input in 65,nm CMOS process. Moreover, power consumption can be reduced because input NMOS and PMOS share bias current. According to the simulation results, for the same power consumption, in the proposed circuit gain-bandwidth product (GBW) is improved by approximately 30% and noise is also reduced in comparison to the conventional topology.

Most previous approaches on comparing the results for software architecture recovery are designed to handle only flat decompositions. In this paper, we propose a novel distance called Split-Jaccard Distance of Hierarchical Decompositions. It extends the Jaccard coefficient and incorporates the concept of the splits of leaves in a hierarchical decomposition. We analyze the proposed distance and derive its properties, including the lower-bound and the metric space.

In this paper, we explore possibilities and difficulties to prove super-quadratic formula size lower bounds from the following aspects. First, we consider recursive Boolean functions and prove their general formula size upper bounds. We also discuss recursive Boolean functions based on exact 2-bit functions. We show that their formula complexity are at least Ω(n2). Hence they can be candidate Boolean functions to prove super-quadratic formula size lower bounds. Next, we consider the reason of the difficulty of resolving the formula complexity of the majority function in contrast with the parity function. In particular, we discuss the structure of an optimal protocol partition for the Karchmer-Wigderson communication game.

During the investment process for enhancing the level of IT security, organizations typically rely on two kinds of security countermeasures, i.e., proactive security countermeasures (PSCs) and reactive security countermeasures (RSCs). The PSCs are known to prevent security incidents before their occurrence, while the RSCs identify security incidents and recover the damaged hardware and software during or after their occurrence. Some researchers studied the effect of the integration of PSCs and RSCs, and showed that the integration can control unwanted incidents better than a single type of security countermeasure. However, the studies were made mostly in a qualitative manner, not in a quantitative manner. In this paper, we focus on deriving a quantitative model that analyzes the influence of different conditions on the efficiency of the integrated security countermeasures. Using the proposed model, we analyze for the first time how vulnerability and the potential exploits resulting from such vulnerability can affect the efficiency of the integrated security countermeasures; furthermore, we analytically verify that as the efficiency of PSCs increases, the burden of RSCs decreases, and vice versa. Also, we describe how to select possibly optimal configurations of the integrated security countermeasures.

Network virtualization is one of the promising technologies that can increase flexibility, diversity, and manageability of networks. Building optimal virtual networks across multiple domains is getting much attention, but existing studies were based on an unrealistic assumption, that is, providers' private information can be disclosed; as is well known, providers never actually do that. In this paper, we propose a new method that solves this multi-domain problem without revealing providers' private information. Our method uses an advanced secure computation technique called multi-party computation (MPC). Although MPC enables existing unsecured methods to optimize virtual networks securely, it requires very large time to finish the optimization due to the MPC's complex distributed protocols. Our method, in contrast, is designed to involve only a small number of MPC operations to find the optimal solution, and it allows providers to execute a large part of the optimization process independently without heavy distributed protocols. Evaluation results show that our method is faster than an existing method enhanced with MPC by several orders of magnitude. We also unveil that our method has the same level of embedding cost.

Recently network bandwidth becomes a performance concern particularly for collective communication since bisection bandwidths of supercomputers become far less than their full bisection bandwidths. In this context we propose the use of a network coding technique to reduce the number of unicasts and the size of data transferred in latency-sensitive collective communications in supercomputers. Our proposed network coding scheme has a hierarchical multicasting structure with intra-group and inter-group unicasts. Quantitative analysis show that the aggregate path hop counts by our hierarchical network coding decrease as much as 94% when compared to conventional unicast-based multicasts. We validate these results by cycle-accurate network simulations. In 1,024-switch networks, the network reduces the execution time of collective communications as much as 70%. We also show that our hierarchical network coding is beneficial for any packet size.

With the rise of component-based software development, its reliability has attracted much attention from both academic and industry communities. Component-based software development focuses on architecture design, and thus it is important for reliability analysis to emphasize software architecture. Existing approaches to architecture-based software reliability analysis don't model the usage profile explicitly, and they ignore the difference between the testing profile and the practical profile of components, which limits their applicability and accuracy. In response to these issues, a new reliability modeling and prediction approach is introduced. The approach considers reliability-related architecture factors by explicitly modeling the system usage profile, and transforms the testing profile into the practical usage profile of components by representing the profile with input sub-domains. Finally, the evaluation experiment shows the potential of the approach.

A narrowband interference (NBI) estimation and mitigation method based on compressive sensing (CS) for communication systems with repeated training sequences is investigated in this letter. The proposed CS-based differential measuring method is performed through the differential operation on the inter-block-interference-free regions of the received adjacent training sequences. The sparse NBI signal can be accurately recovered from a time-domain measurement vector of small size under the CS framework, without requiring channel information or dedicated resources. Theoretical analysis and simulation results show that the proposed method is robust to NBI under multi-path fading channels.

Golf is a solitaire game, where the object is to move all cards from a 5×8 rectangular layout of cards to the foundation. A top card in each column may be moved to the foundation if it is either one rank higher or lower than the top card of the foundation. If no cards may be moved, then the top card of the stock may be moved to the foundation. We prove that the generalized version of Golf Solitaire is NP-complete.

Compressive sensing (CS) exploits the sparsity or compressibility of signals to recover themselves from a small set of nonadaptive, linear measurements. The number of measurements is much smaller than Nyquist-rate, thus signal recovery is achieved at relatively expense. Thus, many signal processing problems which do not require exact signal recovery have attracted considerable attention recently. In this paper, we establish a framework for parameter estimation of a signal corrupted by additive colored Gaussian noise (ACGN) based on compressive measurements. We also derive the Cramer-Rao lower bound (CRB) for the frequency estimation problems in compressive domain and prove some useful properties of the CRB under different compressive measurements. Finally, we show that the theoretical conclusions are along with experimental results.

Coarse-grained Reconfigurable Architecture (CGRA) is a promising mobile computing platform that provides both high performance and high energy efficiency. In an application, loop nests are usually mapped onto CGRA for further acceleration, so optimizing the mapping is an important goal for design of CGRAs. Moreover, obviously almost all of mobile devices are powered by batteries, how to reduce energy consumption also becomes one of primary concerns in using CGRAs. This paper makes three contributions: a) Proposing an energy consumption model for CGRA; b) Formulating loop nests mapping problem to minimize the battery charge loss; c) Extract an efficient heuristic algorithm called BPMap. Experiment results on most kernels of the benchmarks and real-life applications show that our methods can improve the performance of the kernels and lower the energy consumption.

Providing images captured by an on-board camera to surrounding vehicles is an effective method to achieve smooth road traffic and to avoid traffic accidents. We consider providing images using WiFi technology based on the IEEE802.11p standard for vehicle-to-vehicle (V2V) communication media. We want to compress images to suppress communication traffic, because the communication capacity of the V2V system is strictly limited. However, there are difficulties in image compression and transmission using wireless communication especially in a vehicular broadcast environment, due to transmission errors caused by fading, packet collision, etc. In this letter, we propose an image transmission technique based on compressed sensing. Through computer simulations, we show that our proposed technique can achieve stable image reconstruction despite frequent packet error.

To represent interactive objects, we propose a choice-disjunctive declaration statement of the form $S add R$ where S, R are the (procedure or field) declaration statements within a class. This statement has the following semantics: request the user to choose one between S and R when an object of this class is created. This statement is useful for representing interactive objects that require interaction with the user.

A processing system with multiple field programmable gate array (FPGA) cards is described. Each FPGA card can interconnect using six I/O (up, down, left, right, front, and back) terminals. The communication network among FPGAs is scalable according to user design. When the system operates multi-dimensional applications, transmission efficiency among FPGA improved through user-adjusted dimensionality and network topologies for different applications. We provide a fast and flexible circuit configuration method for FPGAs of a multi-dimensional FPGA array. To demonstrate the effectiveness of the proposed method, we assess performance and power consumption of a circuit that calculated 3D Poisson equations using the finite difference method.

We fabricated organic field-effect transistors (OFETs) having a thin layer of molybdenum trioxide (MoO$_3$), a Lewis acid, and evaluated their electrical characteristics. The insertion of a thin MoO$_3$ layer reduces the on/off ratio but improves the apparent mobility of the charge carriers. To identify the dominant mechanism responsible for this effect, we characterized devices having a 69-nm-thick pentacene layer with a 1-nm-thick MoO$_3$ layer either between the gold source and the drain electrodes or only directly under these electrodes. The former device exhibited a low on/off ratio, whereas the latter device exhibited an on/off ratio comparable to those of conventional pentacene OFETs without a thin MoO$_3$ layer, suggesting that the formation of charge-transfer (CT) complexes immediately above the conduction channel is the critical mechanism. CT complexes at the pentacene/MoO$_3$ interface immediately above the conduction channel contribute to the formation of an effective channel for off-currents as well as drain currents. Moreover, we also attempted to improve the on/off ratio by using a cloth to rub the surface of a thin MoO$_3$ layer immediately above the conduction channel to create what we believe to be a profile with abrupt changes in height in the direction of the drain current conduction in OFETs. Consequently, it was found that such a rubbed MoO$_3$ layer had a surface with a scratched pattern, and the on/off ratio of the OFET was improved, indicating that controlling the CT complex formation by patterning a MoO$_3$ layer can reduce the off-current in OFETs having a pentacene/MoO$_3$ active layer.

The concept of sparse representation is gaining momentum in image processing applications, especially in image compression, from last one decade. Sparse coding algorithms represent signals as a sparse linear combination of atoms of an overcomplete dictionary. Earlier works shows that sparse coding of images using learned dictionaries outperforms the JPEG standard for image compression. The conventional method of image compression based on sparse coding, though successful, does not adapting the compression rate based on the image local block characteristics. Here, we have proposed a new framework in which the image is classified into three classes by measuring the block activities followed by sparse coding each of the classes using dictionaries learned specific to each class. K-SVD algorithm has been used for dictionary learning. The sparse coefficients for each class are Huffman encoded and combined to form a single bit stream. The model imparts some rate-distortion attributes to compression as there is provision for setting a different constraint for each class depending on its characteristics. We analyse and compare this model with the conventional model. The outcomes are encouraging and the model makes way for an efficient sparse representation based image compression.

This paper seeks to improve power-performance efficiency of embedded systems by the use of dynamic reconfiguration. Programmable logic devices (PLDs) have the competence to optimize the power consumption by the use of partial and/or dynamic reconfiguration. It is a non-exclusive approach, which can use other power-reduction techniques simultaneous, and thus it is applicable to a myriad of systems. The power-performance improvement by dynamic reconfiguration was evaluated through an augmented reality system that translates Japanese into English. It is a wearable and mobile system with a head-mounted display (HMD). In the system, the computing core detects a Japanese word from an input video frame and the translated term will be output to the HMD. It includes various image processing approaches such as pattern recognition and object tracking, and these functions run sequentially. The system does not need to prepare all functions simultaneously, which provides a function by reconfiguration only when it is needed. In other words, by dynamic reconfiguration, the spatiotemporal module-based pipeline can introduce the reduction of its circuit amount and power consumption compared to the naive approach. The approach achieved marked improvements; the computational speed was the same but the power consumption was reduced to around $rac{1}{6}$.

In this paper, we discuss performance modeling of 3-D stencil computing on an FPGA accelerator with a high-level synthesis environment, aiming for efficient exploration of user-space design parameters. First, we analyze resource utilization and performance to formulate these relationships as mathematical models. Then, in order to evaluate our proposed models, we implement heat conduction simulations as a benchmark application, by using MaxCompiler, which is a high-level synthesis tool for FPGAs, and MaxGenFD, which is a domain specific framework of the MaxCompiler for finite-difference equation solvers. The experimental results with various settings of architectural design parameters show the best combination of design parameters for pipeline structure can be systematically found by using our models. The effects of changing arithmetic accuracy and using data stream compression are also discussed.