A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p+ buried layer and a low sheet-resistance extrinsic n+ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm2. Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF2-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.

Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.

A self-induced-transparent (SIT) system that takes advantage of morphology dependent resonances (MDR's) in a Mie-sized microsphere doped with a resonant material is proposed. The present system is doubly resonant: one has microscopic origin (the two-level system), while the other has macroscopic origin (the MDR). In this geometry, owing to the feedback action of MDR's, the pulse area can be much expanded, and thus the electric-field amplitude of the incident pulse can be reduced substantially compared with the conventional one-way SIT propagation. Theoretical results that incorporate dephasing due to structural imperfections are shown.

A new gloss-extracting method is proposed in this study. A spatial filter with variable resolution is used for the extraction of glossiness. Various spheres and cylinders with curvature radii from 4 to mm are used as the specimens. In all samples, a strong correlation, with a correlation coefficient of more than 0.98, has been observed between psychological glossiness Gph perceived by the human eye and glossiness Gfm extracted by this method. This method is useful for plane specimens as well as spherical and cylindrical ones.

Many combinatorial problems can be efficiently solved for partial k-trees (graphs of treewidth bounded by k). The edge-coloring problem is one of the well-known combinatorial problems for which no NC algorithms have been obtained for partial k-trees. This paper gives an optimal and first NC parallel algorithm to find an edge-coloring of any given partial k-tree with bounded degrees using a minimum number of colors. In the paper k is assumed to be bounded.

In the actual sound environmental systems, it seems to be essentially difficult to exactly evaluate a whole probability distribution form of its response fluctuation, owing to various types of natural, social and human factors. We have reported a unified probability density expression in the standard expansion form of Hermite type orthonormal series taking a well-known Gaussian probability density function (abbr. p.d.f.) as the basis for generally evaluating non-Gaussian, non-linear correlation and/or non-stationary properties of the fluctuation phenomenon. However, in the real sound environment, there still remain many actual problems on the necessity of improving the above standard type probability expression for practical use. First, a central point in this paper is focused on how to find a new probabilistic theory of practically evaluating the variety and complexity of the actual random fluctuations, especially through newly introducing an equvivalence transformation toward the standard type probability expression mentioned above in the expansion form of Hermite type orthonormal series. Then, the effectiveness of the proposed theory has been confirmed experimentally too by applying it to the actual problems on the response probability evaluation of various sound insulation systems in an acoustic room.

Switched-capacitor chaotic neurons fabricated in a full-custom integrated circuit are used to investigate the behavior of 2- and 3-neuron chaotic neural networks. Various sets of parameters are used to visualize the dynamical responses of the networks. Hysteresis of the network is also demonstrated. Lyapunov exponents are approximated from the measured data to characterize the state of each neuron. The effect of the finite length of data and the rounding effect of data acquisition system to the computation of Lyapunov exponents are briefly discussed.

This paper deals with an efficient radix-2 divider design theory that uses carry-propagation-free adders based on redundant binary{1, 0, 1} representation. In order to compute the division fast, we look ahead to the next step quotient-digit selection embedded in the current partial remainder calculation. The solution is a function of the four most significant digits of the current partial remainder, when scaling the divisor in the range [1, 9/8). In gate depth, this result is better than the higher radix-4 case without the look-ahead quotient-digit selection and the design is simple.

A graph G is said to be universal for a family F of graphs if G contains every graph in F as a subgraph. A minimum universal graph for F is a universal graph for F with the minimum number of edges. This paper considers a minimum universal graph for the family Fkn of graphs on n vertices with path-width at most k. We first show that the number of edges in a universal graph Fkn is at least Ω(kn log(n/k)). Next, we construct a universal graph for Fkn with O(kn log(n/k)) edges, and show that the number of edges in a minimum universal graph for Fkn is Θ(kn log(n/k)) .

In this paper, we report a new approach about parsing and searching problem for a given phonetic lattice. The approach is based on the Divide and Conquer (DC) strategy. By dividing the phonetic lattice, we first construct a PD-tree to represent this lattice, then, we parse through this PD-tree to identify the possible sentence which is supposed to be the speech utterance. Next, we propose a new search scheme called Downward Request (DR) search model to decrease the computation costs, and this search model gives us the optimal or N-best solutions. Experiments performed on Chinese speech recognition show us the good results.

The Manchester Dataflow Machine (MDFM) works with tasks of size equal to one single instruction. This fine granularity aims at exploring all parallelism at the instruction level. However, this project decision increases the instruction communication cost, which ends up to jam the interconnection network and reduces the system performance. One way to skirt this problem is to adopt variable size tasks instead of working with such small task size. In this paper, in order to study whether or not the usage of such variable size tasks in the MDFM architecture contributes to the improvement of the performance, some simulations by toy programs take place. In the simulation, variable size tasks are realized by packing the sequential instruction stretches into one task. To manage this packing, the Sequential Block (SB) technique is developed. The simulation of those packed and unpacked programs give an outline of advantages and disadvantages of working with variable size tasks, and how the SB technique should be implemented in the system.

The design procedure of a multithreaded processor dedicated to the image generation is described, which can be achieved by means of a high-level synthesis tool PARTHENON. The processor employs a multithreaded architecture which is a novel promising approach to the parallel image generation. This paper puts special stress on the high-level synthesis scheme which can simplify the behavioral description for the structure and control of a complex hardware, and therefore enables the design of a complicated mechanism for a multithreaded processor. Implementation results of the synthesis are also shown to demonstrate the performance of the designed processor. This processor greatly improves the throughput of the image generation so far attained by the conventional approach.

We developed an eye-contact technique using a blazed half-transparent mirror (BHM), which is a micro-HM array arranged on the display surface, to make a compact eye-contact videophone. This paper describes a new BHM structure that eliminates ghosts and improves image quality. In the new BHM, the reflection and transmission areas are separated to exclude ghosts from appearing in the captured image. We evaluated the characteristics of the captured and displayed images. The results show that the contrast ratio of the captured image and the brightness of both captured and displayed images are much better than with the previous BHM.

This paper describes the fabrication of 0.1 µm gate length CMOS devices and analysis of delay time by circuit simulation. In order to reduce the gate resistance, TiN capped cobalt salicide technology is applied to the fabrication of 0.1 µm CMOS devices. Gate sheet resistance with a 0.1 µm gate is as low as 5 Ω/sq. Propagation delay times of 0.1 µm and 0.15 µm CMOS inverter are 21 ps and 36 ps. Simulated propagation delay time agreed fairly well with experimental results. For gate length over 0.15 µm, intrinsic delay in CMOS devices is the main dalay factor. This suggests that increasing current drivability is the most efficient way to improve propagation delay time. At 0.1 µm, each parasitic component and intrinsic delay have similar contributions on device speed due to the short channel effect. To improve delay time, we used rapid thermal annealing or a high dose LDD structure. With this structure, drain current increases by more than 1.3 times and simulation predicted a delay time of 28 ps is possible with 0.15 µm CMOS inverters.

A parallel overlapping preconditioner is applied to ICCG method and the effect of the parallel preconditioning on the convergence of the method is investigated by solving large scale block tridiagonal linear systems arising from the discretization of Poisson's equation. Compared with the original ICCG method, the parallel preconditioned ICCG method can solve the problems in high parallelism with slight increasing the number of iterations. Furthermore, the speedup and the efficiency are evaluated for the parallel preconditioned ICCG method by substituting the experimental results into formulae of complexity. For example, when a domain of simulation is discretized on a 250250 rectangular grid and the preconditioner is divided into 249 smaller ones, its speedup is 146.3 with the efficiency 0.59.

We model a road network as a directed graph G(V,E) with a source s and a sink t, where each edge e has a positive length l(e) and each vertex v has a distribution function αv with respect to the traffic entering and leaving v. This paper proposes a polynomial time algorithm for evaluating the importance of each edge e E whicn is defined to be the traffic f(e) passing through e in order to assign the required traffic Fst(0) from s to t along only shortest s-t paths in accordance with the distribution function αv at each vertex v.

We give an efficient shortest path algorithm on a mesh-connected processor array for nn banded matrices with bandwidth b. We use a b/2b/2 semisystolic processor array. The input data is supplied to the processor array from the host computer. The output from the processor array can be also supplied to itself through the host computer. This algorithm computes all pair shortest distances within the band in 7n4b/21 steps.

In this paper, bifurcation and chaotic behavior which occur in simple looped MOS inverters with high speed operation are described. The most important point in this work is to change a nonlinear transfer characteristic of a MOS inverter to the nonlinearity generating a chaos. Three types of circuits which include four, three and one MOS inverters, respectively, are proposed. A switched capacitor (SC) circuit to operate sampling holding is added in the loop in each of the circuits. The bifurcation and chaotic behavior have been found along with a variation of an external input, and/or a sampling clock frequency. The bifurcation and chaotic behavior of the proposed simple looped MOS inverters are verified by employing SPICE circuit simulator as well as the experiments. For the first type of four looped CMOS inverters, Lyapunov exponent λ which has the positive regions for the chaotic behavior can be calculated by use of the fitting nonlinear function synthesized from two sigmoid functions. For the second type of three looped CMOS inverters and the third type of one looped MOS inverter, the nonlinear charge/discharge characteristics of the hold capacitor in the SC circuit is utilized efficiently for forming the nonlinearity generating the bifurcation and chaotic behavior. Their bifurcation can be generated by the sampling clock frequency parameter which is controlled easily.

The blazing effects of dielectric grating consisting of two adjacent sinusoidally modulated layers which lead to the asymmetric profiles on a substrate are analyzed by using improved Fourier series expansion method. This method can be applied to the wide range of grating structure and gave high accurate results by comparing with those obtained by previous method. In this paper, the efficient blazing effects can be achieved by varying normalized distance (w/p) and the normalized thickness (d1/D), where D is kept fixed. The results are greater than those of trapezoidal profiles and triangular profiles. The influences of the second order of modulation index on the radiation efficiencies and normalized leakage factor are also discussed.

The performance of the hybrid-ARQ scheme with a convolutional code, in which the retransmission criterion is based on an estimated decoding error rate, is evaluated for moderately time-varying channels. It is shown by computer simulations that the simple average diversity combining scheme can almost attain the same performance as the optimally weighted diversity combining scheme. For the whole and partial retransmission schemes with the average diversity combining, the theoretical bounds of throughput and bit error rate are derived, and it is shown that their bounds are tight and the treated schemes can attain a given error rate with good throughput for moderately time-varying channels. Furthermore, the throughput is shown to be improved by the partial retransmission scheme compared with the whole retransmission scheme.