A simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances.

We developed a parallel bordered-block-diagonal (BBD) matrix solution for parallel circuit simulation. In parallel circuit sumulation on a MIMD parallel computer, a circuit is partitioned into as many subcircuits as the processors of a parallel computer. Circuit partition produce a BBD matrix. In parallel BBD matrix solution, diagonal blocks are easily solved separately in each processor. It is difficult, however, to solve the interconnection (IC) submatrix of a BBD matrix effectively in parallel. To make matters worse, the more a circuit is partitioned into subcircuits for highly parallel circuit simulation, the larger the size of an IC submatrix becomes. From an examination, we found that an IC submatrix is more dense (about 30% of all entries are non-zeros) than a normal circuit matrix, and the non-zeros per row in an IC submatrix are almost constant with the number of subcircuits. To attain high-speed circuit simulation, we devised a data structure for BBD matrix processing and an approach to parallel BBD matrix solution. Our approach solves the IC submatrix in a BBD matrix as well as the diagonal blocks in parallel using all processors. In this approach, we allocate an IC submatrix in block-wise order rather than in dot-wise order onto all processors. Thus, we balance the processor perfomance with the communication capacity of a parallel computer system. When we changed the block size of IC submatrix allocation from dot-wise order to 88 block-wise order, the 88 block-wise order allocation almost halved the matrix solution time. The parallel simulation of a sample circuit with 3277 transistors was 16.6 times faster than a single processor when we used 49 processors.

An efficient algorithm is presented for finding all solutions of piecewise-linear resistive circuits containing sophisticated transistor models such as the Gummel-Poon model or the Shichman-Hodges model. When a circuit contains these nonseparable models, the hybrid equation describing the circuit takes a special structure termed pairwise-separability (or tuplewise-separability). This structure is effectively exploited in the new algorithm. A numerical example is given, and it is shown that all solutions are computed very rapidly.

Throughout the paper, the nearest-neighbour (NN) interconnection of switches within a multistage interconnection network (MIN) is analysed. Three main results are obtained: (1) The switch preserving transformation of a 2-D MIN into the 1-D MIN (and vice versa) (2) The rearrangeability of the MIN and (3) The number of stages (NS) for the rearrangeable nonblocking interconnection. The analysis is extended to any dimension of the interconnected data set. The topological equivalence between 1-D MINs with NN interconnections (NN-MINs) and 1-D cellular arrays is shown.

This paper presents an analysis of the control characteristics of the series resonant converter with a parallel resonant circuit, especially under parallel resonant frequency. Operations of the circuit are classified into several modes. The control characteristics are calculated using the equations derived from equivalent circuits, and are verified by the experiments. From the analysis, the mechanism of a jumping phenomenon in the closed-loop control characteristics is clarified.

This paper describes a new clustering approach for VLSI placement, which is based on a fractal dimension analysis for the topological structure of modules in a logic diagram. A distinctive feature of this approach is that a measure of the 'fractal dimension' has been introduced into a logic diagram in such a way that the clustering of modules is iterated while the fractal dimension among clustered modules is retained in a prescribed range. A part of experimental results is also shown, which demonstrates that our clustering approach raises the placement performance much higher than the conventional clustering methods.

The graph bisection problem is to partition a given graph into two subgraphs with equal size with minimizing the cutsize. This problem is NP-hard, and hence several heuristic algorithms have been proposed. Among them, the Kernighan-Lin algorithm and the Fiduccia-Mattheyses algorithm are well known, and widely used in practical applications. Since those algorithms are iterative improvement algorithms, in which the current solution is iteratively improved by interchanging a pair of two nodes belonging to different subgraphs, or moving one node from one subgraph to the other, those algorithms tend to fall into a local optimum. In this paper, we present a heuristic algorithm based on subgraph migration to avoid falling into a local optimum. In this algorithm, an initial solution is given, and it is improved by moving a subgraph, which is effective to reduce the cutsize. The algorithm repeats this operation until no further improvement can be achieved. Finally, the balance of the bisection is restored by moving nodes to get a final solution. Experimental results show that the proposed algorithm gets better solutions than the Kernighan-Lin and Fiduccia-Mattheyses algorithms.

This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm2 and consumes 350 mW.

A particle trajectory estimation method from far electromagnetic fields are discussed in this paper. Authors have already presented a trajectory estimation method for single particle system and good agreements between a source particle trajectory and an estimated one have been obtained. For this, this paper discusses twin particles system as an examples of multi-particles systems for simplicity. First of all, it is pointed out that far electromagnetic fields from the twin particles system show quite different aspect from the single particle system using an example, radiation patterns produced by two particles which carry out circular motion. This result tells us that any trajectory estimations for general multi-particles system are almost impossible. However, it is shown that when the distance between the particles is small, the estimation method for the single particle system can be applied to the twin particles system, and that twin particles effects appear as disturbance of estimated trajectory.

This paper presents a modified disparity measurement to recover the depth and a robust method to estimate motion parameters. First, this paper considers phase correspondence for the computation of disparity. It has less computation for disparity than previous methods that use the disparity from correspondence and from correlation. This modified disparity measurement uses the Gabor filter to analyze the local phase property and the exponential filter to analyze the global phase property. These two phases are added to make quasi-linear phases of the stereo image channels which are used for the stereo disparity finding and the structure recovery of scene. Then, we use feature-based correspondence to find the corresponding feature points in temporal image pair. Finally, we combine the depth map and use disparity motion stereo to estimate 3-D motion parameters.

Recently actual use of the OSI standardized protocols has begun on client-server systems of LANs, and reduction of OSI protocol overheads in high-speed networks has become more important. We studied a parallel-processing architecture for Message Handling System (MHS), which requires a large amount of protocol processing and is expected to be used widely. We implemented a prototype MHS server with performance scalable to number of CPUs, by porting an existing MHS software with minimum modification. This paper reports on the parallel processing scheme, hardware and software architecture of the prototype, as well as evaluation of the scheme based on measurement and simulation.

The warp model of the extended Hough transform (EHT) has been proposed to design the explicit expression of the transform function of EHT. The warp model is a skewed parameter space (R(µ,ξ), φ(µ,ξ)) of the space (µ,ξ), which is homeomorphic to the original (ρ,θ) parameter space. We note that the introduction of the skewness of the parameter space defines the angular and positional sensitivity characteristics required in the detection of lines from the pattern space. With the intent of contributing some solutions to basic computer vision problems, we present theoretically a dynamic and centralfine/peripheral-coarse camera vision architecture by means of this warp model of Hough transform. We call this camera vision architecture askant vision' from an analogy to the human askant glance. In this paper, an outline of the EHT is briefly shown by giving three functional conditions to ensure the homeomorphic relation between (µ,ξ) and (ρ,θ) parameter spaces. After an interpretation of the warp model is presented, a procedure to provide the transform function and a central-coarse/peripheralfine Hough transform function are introduced. Then in order to realize a dynamic control mechanism, it is proposed that shifting of the origin of the pattern space leads to sinusoidal modification of the Hough parameter space.

A new algorithm, which is incorporated into the waveform relaxation analysis, for efficiently simulating the transient response of single lossy transmission lines or lossy coupled multiconductor transmission lines, terminated with arbitrary networks will be presented. This method exploits the inherent delay present in a transmission line for achieving simulation efficiency equivalent to obtaining converged waveforms with a single iteration by the conventional iterative waveform relaxation approach. To this end we propose 'line delay window partitioning' algorithm in which the simulation interval is divided into sequential windows of duration equal to the transmission line delay. This window scheme enables the computation of the reflected voltage waveforms accurately, ahead of simulation, in each window. It should be noted that the present window partitioning scheme is different from the existing window techniques which are aimed at exploiting the non–uniform convergence in different windows. In contrast, the present window technique is equivalent to achieving uniform convergence in all the windows with a single iteration. In addition our method eliminates the need to simulate the transmission line delay by the application of Branin's classical method of characteristics. Further, we describe a simple and efficient method to compute the attenuated waveforms using a particular form of lumped element model of attenuation function. Simulation examples of both single and coupled lines terminated with linear and nonlinear elements will be presented. Comparison indicates that the present method is several times faster than the previous waveform relaxation method and its accuracy is verified by the circuit simulator PSpice.

This paper proposes new real–time heuristic distributed parallel algorithms for search, which are based on the concepts of propagations and competitions of concurrent waves. These algorithms are characterized by simplicity and clearness of control strategies for search, and distinguished abilities in many aspects, such as real–time performance, wide suitability for searching AND/OR implicit graphs, and ease in hardware implementation.

In general, message passing multiprocessors suffer from communication overhead and shared memory multiprocessors suffer from memory contention. Also, data I/O overhead limits performance. In particular, computer vision tasks that require massive computation are strongly affected by these disadvantages. This paper proposes new parallel architectures for computer vision, a Flexibly (Tightly/Loosely) Coupled Multiprocessor (FCM) and a Flexibly Coupled Hypercube Multiprocessor (FCHM) to alleviate these problems. FCM and FCHM have a variable address space memory in which a set of neighboring memory modules can be merged into a shared memory by a dynamically partitionable topology. FCM and FCHM are based on two different topologies: reconfigurable bus and hypercube. The proposed architectures are quantitatively analyzed using computational models and parallel vision algorithms are simulated on FCM and FCHM using the Intel's Personal SuperComputer (iPSC), a hypercube multiprocessor, showing significant performance improvements over that of iPSC.

We discuss a processor scheduling problem for parallel logic simulation of combinational circuits. In the processor scheduling problem, to be discussed in this paper, for logic simulation using time–first method, the time needed for each gate evaluation is not given beforehand, and is not constant. This feature distinguishes the processor scheduling problem from typical task scheduling problems. First, we devise newly Algorithm MET to solve the processor scheduling problem. The key idea of Algorithm MET is to determine processor scheduling incrementally and dynamically. Then, experimental evaluations using well–known twelve benchmark combinational circuits show the usefulness of Algorithm, MET, compared with conventional static algorithms. We believe that this is a first step to implement parallel logic simulation of combinational circuits.

An optimal control theory has been applied to a biological compartment system to show a method to analyze the control principle of biological system represented by compartments. Present theory has been proposed to afford a theoretical back ground and validity for the strategy of drug administration or control of the anesthetic agent in practical medicine. The instantaneous change of the concentration of a given material within a biological system has been expressed by differential equations. Each compartment has been set to be transferred a material from all other compartments and conversely each compartment sends it to all other compartments. The control input was restricted to be one kind. The performance function involved the deviation from the target value, the rate of change in concentration and the amount of the control variables. The biological system was defined to operate optimally only when the performance function has been minimized during a given time period. By the optimal control theory of Pontoriagin, above biological problem has been converted to a mathematical problem and was solved numerically by multiple shooting method. The calculated trajectory of the optimal control has been asymmetric parabolic one with the maximum at its initiation and the minimum at the middle of total reaction time. This pattern has been consistent with that of probable transient change of the concentration of anesthetic agent when it has been inhalated under the most up to date "Rapid Inhalation Induction" method. The optimal trasient change of the concentration at each compartment has beeb affected by the difference in time dependent nature and the magnitude of the transfer rate. Present theory afforded a method to analyze the control strategy of biological system expressed by compartments model and showed an availability for actual clinical medicine. The optimal control principle must be a most adequate one to describe the Homeostasis in biological system.

In the conventional protocol synthesis, it is generally assumed that primitives in service specifications cannot be executed simultaneously at different Service Access Points (SAPs). Thus if some primitives are executed concurrently, then protocol errors of unspecified receptions occur. In this paper, we try to extend a class of service specifications from which protocol specifications are synthesized by the previous methods. We first introduce priorities into primitives in protocol specification so that it always selects exactly one primitive of the highest priority from a set of primitives that can be executed simultaneously, and executes it. Then, based on this execution ordering, we propose a new protocol synthesis method which can avoid protocol errors due to message collisions, communication competitions and so on. By applying the proposed synthesis method, we can automatically synthesize a protocol specifications from a given service specification which includes an arbitraty number of processes and allows parallel execution of primitives.

A globally and quadratically convergent algorithm is presented for solving nonlinear resistive networks containing transistors modeled by the Gummel-Poon model or the Shichman-Hodges model. This algorithm is based on the Katzenelson algorithm that is globally convergent for a broad class of piecewise-linear resistive networks. An effective restart technique is introduced, by which the algorithm converges to the solutions of the nonlinear resistive networks quadratically. The quadratic convergence is proved and also verified by numerical examples.

In a distributed system, the protocol entities must exchange some data values and synchronization messages in order to ensure the temporal ordering of the events described in a service specification for the distributed system. It is desirable that a correct protocol specification can be derived automatically from a given service specification. In this paper, we propose an algorithm which synthesizes automatically a correct protocol specification from a service specification described as a Marked Graph with Registers (MGR) model and resources (registers and gates) allocation information. This model has a finite control modeled as a marked graph. Therefore, parallel events can be described. In our method, to minimize the number of the exchanged messages, we use a procedure to calculate an optimum solution for 0-1 integer linear programming problems. The number of the steps which each protocol entity needs to simulate one transition in the service specification is also minimized. Ways to avoiding conflict of registers are also described. Our approach has the following advantages. First, parallel events can be described in a service specification. Secondly, many practical systems can be described in the MGR model. Finally, at the protocol specification level, we can understand what events can be executed in parallel.