The scaling laws between the design rules and the smallest sizes and numbers of particles capable of causing pattern defects and scrapping dies in semiconductor device manufacturing are described. Simulation with electromagnetic waveguide model indicates the possibility that particles, the sizes of which are of comparable order or even smaller than the wavelength of the lithography irradiation sources, are capable of causing pattern defects. For example, in the future 0.25 µm-design-rule era, the critical sizes of Si, Al, and SiO2 particles are simulated as 120 nm 120 nm, 120 nm 120 nm, and 560 nm 560 nm, respectively, in the case of 0.7 µm-thick chemically-amplified positive photoresist with 47 nm-thick top anti-reflective coating films. Future giga-scale integration era is also predicted.

This paper proposes a new method to design an optimal pipelined instructions set processor for ASIP development using a formal HW/SW codesign methodology. First, a HW/SW partioning algorithm for selecting an optimal pipelined architecture is outlined. Then, an adaptive detabase approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in the HW/SW partitioning process. The experimental results show that the proposed method is effective and efficient.

Systems for removing particulates and gaseous contaminants using the UV/photoelectron method under atmospheric and low pressure conditions have been investigated and its availability has been demonstrated. From experimental results, more than 90 % of particulate contaminants are removed by this method under atomospheric and low pressure conditions. This method can be used to design superclean spaces for wafer stockers, and wafer delivering systems in the LSI fabrication process.

This paper reviews Dynamic Channel Allocation (DCA) in TDMA cellular systems. The emphasis is on distributed DCA, which features decentralized control and adaptability to interference. Performance measures are discussed not only from a theoretical viewpoint but also from a practical viewpoint. Major techniques to enhance the capacity of cellular systems are channel segregation, reuse-partitioning, and transmitter power control. In addition to the performance of conventional cellular systems, differing performance in microcellular systems and multi-layer cellular systems is also discussed.

An adaptive algorithm for a single sinusoid detection using IIR bandpass filter with parallel block structure has been proposed by Nishimura et al. However, the algorithm has three problems: First, it has several input frequencies being impossible to converge. Secondly, the convergence rate can not be higher than that of the scalar structure. Finally, it has a large amount of computation. In this paper, a new algorithm is proposed to solve these problems. In addition, a new structure is proposed to reduce the amount of computation, in which the adaptive control signal generator is realized by the paralel block structure. Simulation results are given to illustrate the performance of the proposed algorithm.

Throughout the paper, the proper operating of the self-routing principle in 2-D shuffle multistage interconnection networks (MINs) is analysed. (The notation 1-D MIN and 2-D MIN is applied for a MIN which interconnects 1-D and 2-D data, respectively.) Two different methods for self-routing in 2-D shuffle MINs are presented: (1) The application of self-routing in 1-D MINs by a switch-pattern preserving transformation of 1-D shuffle stages into 2-D shuffle stages (and vice versa) and (2) the general concept of self-routing in 2-D shuffle MINs based on self-routing with regard to each coordinate which is the original contribution of the paper. Several examples are provided which make the various problems transparent.

A simplified distribution base resistance model (SDM) is proposed to identify each component of the base resistance and determine the dominant. This model divides the parasitic base resistance into one straight path and two surrounding paths. It is clarified that the link base resistance is dominant in a short emitter and the surrounding polysilicon base electrode resistance is dominant in a long emitter. In the SDM, the distance of the link base is reduced to half; with metal silicide as the extrinsic base electrode, the base resistance will be reduced to 75%.

A trained sparse conjugate codebook is proposed for improving the speech quality of CELP-based coding in a noisy environment. Although CELP coding provides high quality at a low bit rate in a silent environment (creating clean speech), it cannot provide a satisfactory quality in a noisy environment because the conventional fixed codebook is designed to be suitable for clean speech. The proposed codebook consists of two sub-codebooks; each sub-codebook consists of a random component and a trained component. Each component has excitation vectors consisting of a few pulses. In the random component, pulse position and amplitude are determined randomly. Since the radom component does not depend on the speech characteristics, it handles noise better than the trained one. The trained component maintains high quality for clean speech. Since excitation vector is the sum of the two sub-excitation vectors, this codebook handles various speech conditions by selecting a sub-vector from each component. This codebook also reduces the computational complexity of a fixed codebook search and memory requirements compared with the conventional codebook. Subjective testing (absolute category rating (ACR) and degradation category rating (DCR)) indicated that this codebook improves speech quality compared with the conventional trained codebook for noisy speech. The ACR test showed that the quality of the 8 kbit/s CELP coder with this codebook is equivalent to that of the 32 kbit/s ADPCM for clean speech.

A novel reactive congestion control scheme based on Dynamic UPC/NPC (Usage/Network Parameter Control) in ATM networks is proposed. In this scheme, policing parameters at the UPC/NPC are dynamically modified in response to the reception of RM (Resource Management) cells. In a congested state, traffic volume submitted to the network is regulated by Dynamic UPC/NPC, while providing negotiated QoS (Quality of Service) for each ATM connection. When end-stations (or edge-entities between network segments) operate according to ER-based (Explicit Rate based) behavior, a UPC/NPC function will indicate (send) an ER value toward each source end-station using backward RM cells. In this case, the policing parameter at the UPC/NPC should take the same value as the ER value. When end-stations (or edge-entities) operate according to EFCI-based (Explicit Forward Congestion Indication based) behavior, the modified policing parameter at the UPC/NPC point must be harmonized with the modified cell transmission rate at the source end-stations (or at the edge-entities). In order to improve the control performance for the long distance connections, backward RM cells will be generated by the NPC function (UPC function will be optional) at the egress of a congested network in response to the reception of EFCI marked cells (or forward RM cells) as a proxy destination end-station, and they will be sent back toward the UPC/NPC function at the ingress of the network. As a result, the proposed control scheme enables the network to recover from the congested state securely and provide the negotiated service quality, even if cooperation of (rate-based) flow control at each source end-station (and at edge-entities between network segments) is not expected.

In ATM networks Connection Admission Control (CAC) is a key part of traffic control but several challenging problems still remain. One is how to assign sufficient bandwidth fast enough to achieve real-time CAC. Although solutions to the bandwidth assignment problem have been proposed, they require a lot of calculations depending on the number of VCs and on the number of different VC types. Therefore, it is difficult to apply these solutions to real-time CAC decisions, This paper presents a cell-loss ratio evaluation algorithm that takes the peak and the average cell rates as inputs, and providers the upper-bound of the cell-loss ratio. The most remarkable characteristic of this algorithm is that it does not require exhaustive calculation and its calculation load is independent of the number of VCs and the number of different VC types. Using this approximation, we propose a real-time CAC. The experimental results show that call processing of the proposed CAC using a processor, whose pertormance is almost the same as that of a processor in a conventional PBX, terminates within several milliseconds.

This work addresses the problems of bit allocation and coding gain in subband coding system with non-paraunitary filter banks. Since energy conservation does not hold in non-paraunitary filter banks, the model to be adopted for quantizers is important to evaluate the output distortion introduced by subband signal quantization. To evaluate the overall distortion we start with adopting the gain plus additive noise model for quantizers, which is more reliable than the additive noise model. With this model, the expression for overall reconstruction error variance becomes so complicated that the problem of optimum bit allocation, as required for evaluation of the coding gain, must be numerically solved. So, we propose an approximation method in which we neglect the terms due to correlation among quantization errors in calculating the bit allocation but take them into consideration in evaluating the coding gain, assuming sufficiently high bitrate coding. Application of this approximation method to the SSKF subband coding systems with AR (1) input source shows that the method is very accurate even at low bit rate coding (1 bit/sample).

A learning algorithm is presented for nearest neighbor pattern classifiers for the cases where mixed supervised and unsupervised training data are given. The classification rule includes rejection of outlier patterns and fuzzy classification. This partially supervised learning problem is formulated as a multiobjective program which reduces to purely super-vised case when all training data are supervised or to the other extreme of fully unsupervised one when all data are unsupervised. The learning, i. e. the solution process of this program is performed with a gradient method for searching a saddle point of the Lagrange function of the program.

A goal of a broadband ISDN network is to provide integrated transport for a wide range of applications such as teleconferencing, entertainment video, and file distribution. These require multipoint communications in addition to conventional point-to-point connections. The essential component to provide multipoint communications is a multicast packet switch. In this paper, we propose and analyze a new parallel multicast packet switch which easily approaches a maximum throughput of 100% as the number of fanout and multicast rate are increased. The proposed switch consists of a simple ring network and a point-to-point switch network in parallel. The ring network provides both replication and routing of multicast packets. The point-to-point switch network is responsible for delivering only unicast packets. The ring network provided in this switch overcomes the problems of clock synchronization and unfairness of access in the slotted ring by synchronizing the ring to the time slot used in the point-to-point switch and providing small amount of speed-up. Moreover, the significant drawbacks of the basic cascaded multicast fabric design are removed in this parallel switch which can separate the unicast and multicast packets before entering the switch fabric. The performance analysis shows that this switch with the small size of input/output buffers achieves good performance in delay and throughput, and the packet loss probability less than 10-9.

Parallel processing is a well-known approach to enhance the performance of communication subsystems. The several forms of parallelism embedded in communication protocols have been applied to the OSI protocol stack. However, the OSI protocol stack involves sequential processing due to the layered architecture. Thus, all the layers have been prevented from performing immediate processing as soon as the data arrives. To solve the problem, we apply a Multiple Instruction Single Data (MISD) parallel scheme to OSI processing for the network layer through the presentation layer. In the MISD scheme, different processors can be allocated to different layers and concurrently run the code for each layer. In contrast, the conventional approach adopts for a pipeline scheme that all the layers can be assigned to different pipeline stages and will be performed in a time interval and their dependence. The implementations have been performed to compare the pipeline scheme with the MISD scheme on the Parsytec Super Cluster consisting of 64 Transputers. The measures show that the MISD scheme has performance improvement as high as about 84% in comparison with the pipeline one.

The properties of the optical-microwave mixing process are investigated in detail. To describe these processes a new approach, the parametric method is introduced which provides a better description of the mixing phenomenon. The paper presents new experimental results on and new theoretical analysis methods for the optical-microwave mixing process and also for its dynamic behavior. The dynamic properties are very important in many applications when the light is intensity modulated by a high frequency or high bit rate signal. A remarkable decrease is observed in the mixing product with increasing optical modulation frequency. There are two reasons for it: the time constant exhibited by the depletion region between the substrate and the epitaxial layer and the optically induced substrate current which is increasing with the modulation frequency and doesn't contribute to the mixing effect. Understanding the optical-microwave mixing process provides new solutions for many applications. For example the optical-microwave mixing techniques offers several advantages in case of optical reception. In the detection process the modulation signal can be transposed to an intermediate frequency band (instead of the baseband) making possible a lower noise reception in a wider band. Another important and advantageous application is in the reception of subcarrier modulated optical signals.

This paper presents efficient algorithms for updating moving octrees with real-time performance. The first algorithm works for octrees undergoing both translation and rotation motion; it works efficiently by compacting source octrees into a smaller set of cubes (not necessarily standard octree cubes) as a precomputation step, and by using a fast, exact cube/cube intersection test between source octree cubas and target octree cubes. A parallel version of the algorithm is also described. Finally, the paper presents an efficient algorithm for the more limited case of octree translation only. Experimental results are given to show the efficiency of the algorithms in comparison to competing algorithms. In addition to being fast, the algorithms presented are also space efficient in that they can produce target octrees in the linear octree representation.

CAMs (Content Addressable Memories) are functional memories which have functions such as word-parallel equivalence search, bilateral 1-bit data shifting between consecutive words, and word-parallel writing. Since CAMs can be integrated because of their regular structure, massively parallel CAM functions can be executed. Taking advantage of CAMs, Ishiura and Yajima have proposed a parallel fault simulation algorithm using a CAM. This algorithm, however, requires a large amount of CAM storage to simulate large-scale circuits. In this paper, we propose a new massively parallel fault simulation algorithm requiring less CAM storage, and compare it with Ishiura and Yajima's algorithm. Experimental results of the algorithm on CHARGE --the CAM-based hardware engine developed in our laboratory--are also reported.

This paper presents a new approach of data pipelining for mincut partitioning acceleration using a parallel computer. When using a parallel computer, it is important to have many processors always active, also the quality of the partitioning must not be sacrificed. Out approach covers both speed and quality. We choose the hardware CAD accelerator TP5000 to implement our approach, which consists of dedicated Very Long Instruction Word (VLIW) processors with high-speed interconnections. The TP5000 allows its connections to be reconfigured to optimize the data pipelines. We estimate that the speed of our approach using 10 processors on the TP5000 is 30 times faster than a SPARCStation-10.

In circuit partitioning for FPGAs, partitioned signal nets are connected using I/O blocks, through which signals are coming from or going to external pins. However, the number of I/O blocks per chip is relatively small compared with the number of logic-blocks, which realize logic functions, accommodated in the FPGA chip. Because of the I/O block limitation, the size of a circuit implemented on each FPGA chip is usually small, which leads to a serious decrease of logic-block utilization. It is required to utilize unused logic-blocks in terms of reducing the number of I/O blocks and realize circuits on given FPGA chips. In this paper, we propose an algorithm which partitions an initial circuit into multi-FPGA chips. The algorithm is based on recursive bi-partitioning of a circuit. In each bi-partitioning, it searches a partitioning position of a circuit such that each of partitioned subcircuits is accommodated in each FPGA chip with making the number of signal nets between chips as small as possible. Such bi-partitioning is achieved by computing a minimum cut repeatedly applying a network flow technique, and replicating logic-blocks appropriately. Since a set of logic-blocks assigned to each chip is computed separately, logic-blocks to be replicated are naturally determined. This means that the algorithm makes good use of unused logic-blocks from the viewpoint of reducing the number of signal nets between chips, i.e. the number of required I/O blocks. The algorithm has been implemented and applied to MCNC PARTITIONING 93 benchmark circuits. The experimental results demonstrate that it decreases the maximum number of I/O blocks per chip by a maximum of 49% compared with conventional algorithms.

This paper proposes a new method to design an optimal pipelined instruction set processor using formal HW/SW codesign methodology. A HW/SW partitioning algorithm for selecting an optimal pipelined architecture is introduced. The codesign task addressed in this paper is to find a set of hardware implemented operations to achieve the highest performance of an ASIP with pipelined architecture under given gate count and power consumption constraints. The problem formalization as well as the proposed algorithm can be considered as an extension of our previous work toward a pipelined architecture. The experimental results show that the proposed method is quite effective and efficient.