This paper proposes a reconfigurable parallel processor based on a two-dimensional linear celular automaton model. The processor based on the model can be reconfigured quickly by utilizing the characteristics of the automaton used for its model. Moreover, the processor has short data path length between processing elements compared with the length of the processor based on one-dimensional linear cellular automaton model which has been already discussed. The processing elements of the processor based on the two-dimensional linear cellular automaton model are regarded as cells and the operational states of the processor are treated as the states of the automaton. When faults are detected, the processor can be reconfigured by changing its state under the state transition function of the processor determined by the weighting function of the automaton model. The processor can be reconfigured within a clock period required for making a state transition. This processor is extremely effective for real-time data processing systems required high reliability.

Since its successful launch in February of 1992, the Japan Earth Resources Satellite-1 (JERS-1) has been sending back high resolution images of the earth for various studies, including the investigation of earth resources, the preservation of environments and the observation of coastal lines. Currently, received images are processed using the Earth Resources Satellite Data Information System (ERSDIS). The ERSDIS is a high speed image processing system utilizing an extended cellular array processor as its main processing module. The extended cellular array processor (CAP), consisting of 4096 processing elements configured into a two-dimensional array, is designed to have many parallel processing optimizing capabilities targetting large-scale image processing at a high speed. This paper desctribes a typical image processing flow, the structure of the ERSDIS, and the details of the CAP design.

An efficient algorithm is presented for finding all solutions of piecewise-linear resistive circuits. In this algorithm, a simple sign test is performed to eliminate many linear regions that do not contain a solution. Therefore, the number of simultaneous linear equations to be solved is substantially decreased. This test, in its original form, requires O(Ln2) additions and comparisons in the worst case, where n is the number of variables and L is the number of linear regions. In this paper, an effective technique is proposed that reduces the computational complexity of the sign test to O(Ln). Some numerical examples are given, and it is shown that all solutions can be computed very efficiently. The proposed algorithm is simple and can be easily programmed by using recursive functions.

This letter presents an algorithm named SPM which generates test patterns for single stuck-at faults in synchronous sequential circuits based on a product machine traversal method. The new idea presented in this letter is partitioned image computation combined with a mixed breadth-first/depth-first search. Image computation is carried out in partitioned manner by substituting constant logical values to some input variables. This brings about significant reduction in storage requirement during image computation. A test generator based on SPM achieved 100% fault efficiency for the ISCAS'89 benchmark circuits with not more than 32 flip-flops.

High speed simulation of neural networks can be achieved through parallel implementations capable of exploiting their massive inherent parallelism. In this paper, we show how this inherent parallelism can be effectively exploited on parallel data-driven systems. By using these systems, the asynchronous parallelism of neural networks can be naturally specified by the functional data-driven programs, and maximally exploited by pipelined and scalable data-driven processors. We shall demonstrate the suitability of data-driven systems for the parallel simulation of neural networks through a parallel implementation of the widely used back propagation networks. The implementation is based on the exploitation of the network and training set parallelisms inherent in these networks, and is evaluated using an image data compression network.

Scattering characteristics of a stratified chiral slab, which is composed of dielectric chiral layers of different material properties and thicknesses, are extensively explored. Design considerations for optical filters are also presented for both the cases of normal and oblique incidence. In the analysis, the incident field is assumed to be a plane monochromatic wave of any arbitrary polarization. The transmitted and reflected electric fields are obtained by noting the fact that the electric field inside a chiral medium is expressed as a sum of the left- and right-circularly polarized plane waves of different phase velocities. Then one can describe the power densities and the Stokes parameters of the transmitted and reflected waves in terms of their field components. As is well known,the Stokes parameters characterize every possible state of polarization of a plane wave. Numerical examples are presented to show the effects of chirality on polarization conversion properties of the stratified chiral slab. The cross- and co-polarized powers and the Stokes parameters of the transmitted and reflected waves are computed for the incident wave of perpendicular polarization. The numerical results demonstrate novel depolarization properties of the slab with application to the design of efficient filters active at the optical region. It is seen from the results that the stratified chiral slab acts as a polarization-conversion transmission filter that passes only a cross-polarized component of the transmitted wave at some frequency band. Furthermore, the slab may be utilized as an antireflection filter for both the cross- and co-po1arized components of the reflected wave at the band region.

The paper presents the improvement of out new approach to optimize the process parameter variation, device heat and wire parasitics for analog LSI design by explicitly incorporating various performance estimations into objective functions for placement and routing. To minimize these objective functions, the placement by the simulated annealing method, and maze routing are effectively modified with the perfomance estimation. The improvement results in the excellent performance driven layout for the large size of analog LSIs.

Many simulators in several fields use the finite difference method and they must solve the large sparse linear equations related. Particularly, if we use the direct solution method because of the convergency problem, it is necessary to adopt a method that can reduce the CPU time greatly. The Multi-Step Diakoptics (MSD) method is proposed as a parallel computation method with a direct solution which is based on Diakoptics, that is, a tearing-based parallel computation method for the sparse linear equations. We have applied the MSD algorithm for one, two and three dimensional finite difference methods. We require a parallel schedule that automatically partitions the desired object's region for study, assigns the processor elements to the partitioned regions according to the MSD method, and controls communications among the processor elements. This paper describes a parallel scheduling that was extended from a one dimensional case to a three dimensional case for the MSD method, and the evaluation of the algorithm using a massively parallel computer with distribuled memory(AP1000).

Let U denote a set comprising elements called "keys." The goal of the nearest point problem is to search quickly for a key among some keys x1 , xn that is the nearest to a reference key x under a partial order relation defined as (x, y) (x, z) for x, y, zU if d(x, y)d(x, z) given a wide-sense distance measure d. This article proposes a method of rearranging x1 , xn into a binary perfectly-balanced tree for solving quickly the nearest point problems. Further, computational performances of the proposed method are evaluated experimentally.

The value distribution of the partial autocorrelation of periodic sequences is important for the evaluation of the sequence performances when sequences of long period are used. But it is difficult to find the exact value distribution of the autocorrelation in general. Therefore we derived some properties of the partial autocorrelation for binary m-sequences which may be used to find the exact value distribution.

In this paper, a definitce relation between the TSP's optimal solution and the attracting region in the parameters space of TSP's energy function is discovered. An many attracting region relating to the global optimal solution for TSP is founded. Then a neural network algorithm with the optimized parameters by using Orthogonal Array Table Method is proposed and used to solve the Travelling Salesman Problem (TSP) for 30, 31 and 300 cities and Map-coloring Problem (MCP). These results are very satisfactory.

A coherent communication system using squeezed light is one of candidates for a realization of super-reliable systems. In order to design such a system, it is essential to understand and to analyze modulators mathematically. However, quantum noise of squeezed light has a colored spectrum which changes with respect to phase of a local laser. Therefore the optimization of the relationship between signal and quantum noise spectrums is required at a modulator to obtain the ultimate performance of the communication system. In this paper, some ideas of modulators for squeezed light are proposed and their spectrum transformations are given. After the brief summary of squeezed quantum noise, a new concept which originates from the restriction of the local laser phase is applied to it. This concept makes a problem originated from a colored quantum noise spectrum more serious. It results in the optimization problem for the relationship between the quantum noise spectrum and signal power spectrum. The solution of this problem is also given under the restriction of local laser phase. As a result, a general design theory for coherent communication system using the squeezed light is given.

In this paper, we evaluate the sustained performance of the prototype SHD (Super High Definition) image processing system NOVI- HiPIPE, and discuss the requirements of a real-time SHD image processing system. NOVI- HiPIPE is a parallel DSP system with 128 PEs (Processing Elements), each containing one vector processor, and its peak performance is 15 GFLOPS. The measured performance of this system is at least 100 times higher than that of the Cray-2 (single CPU), but is still insufficient for real-time SHD image coding. When coding SHD moving images at 60 frames per second with the JPEG algorithm, the performance must be at least ten times faster than is now possible with NOVI- HiPIPE. To extract higher performance from a parallel processing system, the system architecture must be suitable for the implemented process. The advantages of NOVI- HiPIPE are its mesh network and high performance pipelined vector processor (VP), one of which is installed on each PE. When most basic SHD image coding techniques are implemented on NOVI- HiPIPE, intercommunication occurs only between directly connected PEs, and its cost is very low. Each VP can efficiently execute vector calculations. which occur frequently in image processing, and they increase the performance of NOVI- HiPIPE by a factor of from 20 to 100. In order to further improve the performance, the speed of memory access and bit operation must be increased. The next generation SHD image processing system must be built around the VP, an independent function block which controls memory access, and another block which executes bit operations. To support the input and output of SHD moving images and the inter-frame coding algorithms, the mesh network should be expanded into a 3D-cube.

A network-topology-independent static task allocation strategy has been designed and implemented for massively parallel computers. For mapping a task graph to a processor graph, this strategy evaluates several functions that represent some intuitively feasible properties or the graphs. They include the connectivity with the allocated nodes, distance from the median of a graph, connectivity with candidate nodes, and the number of candidate nodes within a distance. Several greedy strategies are defined to guide the mapping process, utilizing the indicated function values. An allocation system has been designed and implemented based on the allocation strategy. In experiments we have defined about 1000 nodes in task graphs with regular and irregular topologies, and the same order of processors with mesh, tree, and hypercube topologies. The results are summarized as follows. 1) The system can yield 4.0 times better total communication costs than an arbitrary allocation. 2) It is difficult to select a single strategy capable of providing the best solutions for a wide range of task-processor combinations. 3) Comparison with hypercube-topology-dependent research indicates that our topology-independent allocator produces better results than the dependent ones. 4) The order of computaion time of the allocator is experimentally proved to be O (n2) where n represents the number of tasks.

This paper presents a technique by which any linear CCD camera, be it one with lens distortions, or even one with misaligned lens and CCD, may be calibrated to obtain optimum performance characteristics. The camera-image formation model is described as a polynomial expression, which provides the line-of-sight flat-beam, including the target light-spot. The coefficients of the expression, which are referred to as camera parameters, can be estimated using the linear least-squares technique, in order to minimize the discrepancy between the reference points and the model-driven flat-beam. This technique requires, however, that a rough estimate of camera orientation, as well as a number of reference points, are provided. Experiments employing both computer simulations and actual CCD equipment certified that the model proposed can accurately describe the system, and that the parameter estimation is robust against noise.

This paper proposes new architecture LSIs based on wave-parallel computing to provide an essential solution to the interconnection problems in massively parallel processing. The basic concept is ferquency multiplexing of digital information, which enables us to utilize the parallelism of electrical (or optical) waves for parallel processing. This wave-parallel computing concept is capable of performing several independent binary funtions in parallel with a single module. In this paper, we discuss the design of wave-parallel image processing LSI to demonstrate the feasibility of reducing the number of interconnections among modules.

This paper proposes a multi-layer cellular network in which a self-organizing method is implemented. The network is developed for the purpose of data clustering and recognition. A multi-layer structure is presented to realize the sophisticated combination of several sub-spaces which are spanned by given input characteristic data. A self-organizing method is useful for evaluating the set of clusters for input data without a supervisor. Thus, using these techniques this network can provide good clustering ability as an example for image/pattern data which have complicated and structured characteristics. In addition to the development of this algorithm, this paper also presents a parallel VLSI architecture for realizing the mechanism with high efficiency. Since the locality can be kept among all processing elements on every layer, the system is easily designed without large global data communication.

The matrix whose eigenvectors are the basis vectors of the DCT is introduced. This matrix leads to a convolution-product property using the DCT. Based on the property, the parameter of uniform blur, such as motion blur or out-of-focus blur, is estimated from the local minima of the DCT energy spectrum of a blurred image. Computer experiments confirmed that the DCT is superior to the DFT for estimating the parameter.

Japan's PARTNERS Project, one of the programmes of ISY advocated by UN, has just started. This letter is a brief introduction of the trials being carried out by the partners in the University of Electro-communications under the Project. The focus is on the distance education and training via ETS-V overcoming the geographical extent and the cultural diversity of the Asia-Pacific Region.

We propose a new architecture of Functional Memory type Parallel Processor (FMPP) architectures called bit-parallel block-parallel (BPBP) FMPP. Design details of a prototype BPBP FMPP chip are also shown. FMPP is a massively parallel processor architecture that has a memory-based simple two-dimensional regular array structure suitable for memory VLSI technology. Computation space increases as integration density of memory increases. Computation time does not depend on the number of processors. So far, a bit-serial word-parallel (BSWP) implementation based on a content addressable memory (CAM) is mainly investigated as one of promising architectures of FMPP. In a BSWP FMPP, each word of a CAM works as a processor, and the amount of hardware is minimized by abopting a bit-serial operation, thus maximizing integration scale. The BSWP FMPP, however, does not allow operations between two words, which restriction limits the applicability of the BSWP FMPP. On the other hand, the proposed BPBP FMPP is designed to execute logical and arithmetic operations on two words. These operations are performed simultaneously on every group of words called a block. BPBP FMPP hereby achieves a high performance while maintaining high integration density of the BSWP, and is suitable for various applications.