This paper addresses the problem of estimating the parameters of multivariate ARMA processes by using higher-order statistics called cumulants. The main objective in this paper is to extend the idea of the q-slice algorithm in univariate ARMA processes to multivariate ARMA processes. It is shown for a multivariate ARMA process that the MA coefficient matrices can be estimated up to postmultiplication of a permutation matrix by using the third-order cumulants and of an extended permutation matrix by using the fourth-order cumulants. Simulation examples are included to demonstrate the effectiveness of the proposed method.

This paper introduces some modelling methods of time-varying stochastic process and its linear/nonlinear adaptive identification. Time-varying models are often identified by using a least square criterion. However the criterion should assume a time invariant stochastic model and infinite observed data. In order to adjust these serious different assumptions, some windowing techniques are introduced. Although the windows are usually applied to a batch processing of parameter estimates, all adaptive methods should also consider them at difference point of view. In this paper, two typical windowing techniques are explained into adaptive processing. In addition to the use of windows, time-varying stochastic ARMA models are built with these criterions and windows. By using these criterions and models, this paper explains nonlinear parameter estimation and the property of estimation convergence. On these discussions, some approaches are introduced, i.e., sophisticated stochastic modelling and multi-rate processing.

We present distributed load balancing mechanisms implemented on multiprocessor systems for real time video encoding, which dynamically equalize load amounts among PE's to cope with extensive computing requirements. The loosely coupled multiprocessor system, e.g. a torus connected one, is treated as the objective system. Two decentralized controlled load balancicg algorithms are proposed, and mathematical analyses are provided to obtain some insights of our decentralized controlled mechanisms. We also prove the proposed algorithms are steady and effective theoretically and experimentally.

The Alopex algorithm is presented as a universal learning algorithm for neural networks. Alopex is a stochastic parallel process which has been previously applied in the theory of perception. It has also been applied to several nonlinear optimization problems such as the Travelling Salesman Problem. It estimates the weight changes by using only a scalar cost function which is measure of global performance. In this paper we describe the use of Alopex algorithm for solving nonlinear learning tasks by multilayer feed-forward networks. Alopex has several advantages such as, ability to escape from local minima, rapid algorithmic computation based on a scalar cost function and synchronous updation of weights. We present the results of computer simulations for several tasks, such as learning of parity, encoder problems and the MONK's problems. The learning performance as well as the generalization capacity of the Alopex algorithm are compared with those of the backpropagation procedure, and it is shown that the Alopex has specific advantages over backpropagation. An important advantage of the Alopex algorithm is its ability to extract information from noisy data. We investigate the efficacy of the algorithm for faster convergence by considering different error functions. We show that an information theoretic error measure shows better convergence characteristics. The algorithm has also been applied to more complex practical problems such as undersea target recognition from sonar returns and adaptive control of dynamical systems and the results are discussed.

This paper presents an algorithm which sums up n binary values on an n m reconfigurable mesh in O(log n/(m log m)1/2) time. This algorithm also yields a corollary which states that n binary values can be summed up on an nlog2n/log log n reconfigurable mesh in constant time.

This document describes a proposal for the implementation of a new VLSI neural network technique called Parallel Propagated Targets (PPT). This technique differs from existing techniques because all layer, within a given network, can learn simultaneously and not sequentially as with the Back Propagation algorithm. the Parallel Propagated Target algorithm uses only information local to each layer and therefore there is no backward flow of information within the network. This allows a simplification in the system design and a reduction in the complexity of implementation, as well as acheiving greater efficiency in terms of computation. Since all synapses can be calculated simultaneously it is possible using the PPT neural algorithm, to parallelly compute all layers of a multi-layered network for the first time.

A procedure for preparing a cross-sectional transmission electron microscopy (TEM) micrograph of a specific area is outlined. A specific area in a specimen has been very difficult to observe with TEM, because a particular small area cannot be preselected in the conventional specimen preparation technique using mechanical polishing, dimpling and ion milling. The technique in this paper uses a focused ion beam (FIB) to fabricate a cross-sectional specimen at a desired area. The applications of this specimen preparation technique are illustrated for investigations of particles in the process of fabricating devices and degraded aluminum/aluminum vias. The specimen preparation technique using FIB is useful for observing a specific area. This technique is also useful for shortening the time of specimen preparation and observing wide areas of LSI devices.

This letter extends the Yule-Walker method to the estimation of ARMA parameters from output measurements corrupted by noise. In the proposed method it is assumed that the noise variance and the input are unknown. An algorithm for the estimation of noise variance is, therefore, given. The use of the variance estimation method proposed here together with the Yule-Walker equations allow the estimation of the parameters of a minimum phase ARMA model based only on noisy measurements of its output. Moreover, using this method it is not necessary to slove a set of nonlinear equations for MA parameter estimation as required in the conventional correlation based methods.

We have studied a circuit partitioning approach in the view of parallel circuit simulation on a MIMD parallel computer. In parallel circuit simulation, a circuit is partitioned into equally sized subcircuits while minimizing the number of interconnection nodes. Besides circuit partitioning time should be short enough compared with the total simulation time. From the details of circuit simulation time, we found that balancing subcircuits is critical for low parallel processing, whereas minimizing the interconnection nodes is critical for highly parallel processing. Our circuit partitioning approach consists of four steps： Grouping transistors, initial partitioning the transistor-groups, minimizing the number of interconnection nodes, and balancing the subcircuits. It is based on an algorithmic approach, and can directly control the tradeoffs between balancing subcircuits and minimizing the interconnection nodes by adjusting the parameters. We partitioned a test circuit with 3277 transistors into 4, 9, ... , 64 subcircuits, and did parallel simulations using PARACS, our parallel circuit simulator, on an AP1000 parallel computer. The circuit partitioning time was short enough-less than 3 percent of the total simulation time. The highest performance of parallel analysis using 49 processors was 16 times that of a single processor, and that for total simulation was 9 times.

For the efficient circuit simulation, several direct/relaxation-based mixed mode simulation techniques have been studied. This paper proposes the combination of selective trace, which is well-known in the logic simulation, with dynamic network separation. In the selective trace method, the time points to be analyzed are selected for each subcircuit. Since the separation technique enables the analysis of each subcircuit independently, it is possible to skip solving the latent subcircuits, according to selective trace. Selecting the time points in accordance with activity of each subcircuit is analogous to multirate numerical integration technique used in the waveform relaxation algorithm.

We have investigated the relationship between particle removal efficiency and etched depth in SC-1 solution (the mixture composed of ammonium hydroxide, hydrogen peroxide and DI water) for Si wafers. The Si etching rate increases with increasing NH4OH (ammonium hydroxide) concentration. The particle removal efficiency depends on the etched Si depth, and is independent of NH4OH concentration. The minimum required Si etching depth to get over 95% particle removal efficiency is 4 nm. Particles on the Si wafers exponentially decrease with increasing the etched Si depth. However the particle removal efficiency is not affected by particle size ranging from 0.2 to 0.5 µm. The particle removal mechanism on the Si wafers in SC-1 solution is dominated by the lift-off of particles due to Si undercutting and redeposition of the removed particle.

The stability conditions and stability factors of terminated active two port networks are investigated. They are expressed with the S parameters of active devices and the radii and centers of the circles defined by source and load terminations. The stability conditions are applied to specific cases. Some of the results correspond to the stability conditions expressed in Z, Y, H or G parameters and one of the other stability conditions of terminated two port network is similar to that for passive terminations which is expressed in S parameters. The various results derived in this paper are very useful for checking the stability of amplifiers, because both stability conditions and stability factors are simply calculated by using the S parameters without using the graphical method or transforming S parameters to Z, Y, H or G parameters. These stability conditions can be also used even if negative input or output resistance appears and even if the real part of source or load immittance is negative.

Recently, efficient algorithms that exploit the separability of nonlinear mappings have been proposed for finding all solutions of piecewise-linear resistive circuits. In this letter, it is shown that these algorithms can be extended to circuits containing piecewise-linear resistors that are neither voltage nor current controlled. Using the parametric representation for these resistors, the circuits can be described by systems of nonlinear equations with separable mappings. This separability is effectively exploited in finding all solutions. A numerical example is given, and it is demonstrated that all solutions are computed very rapidly by the new algorithm.

Today, defect sources of LSI device mainly lie in the process equipments. The particles generating in these equipments are introduced onto the wafer, and form the defects resulting in functional failures of LSI device. Thus, reducing these particles is acquired for increasing production yield and higher productivity, and it is important to identify the particle source in the equipment. In this study, we discussed new two methods to identify this source in the equipment used in the production line. The important point of identifing is to estimate the particle generation with short time and high accuracy, and to minimize long time stop of the equipment requiring disassembly. First, we illustrated "particle distribution analysis method." In this method, we showed the procedure to express the particle distribution mathematically. We applied this method to our etching equipment, and could identify the particle source without stopping this etching equipment. Secondly, we illustrated the method of "in-situ particle monitoring method," and applied this method to our AP-CVD equipment. As a result, it was clear the main particle source of this equipment and the procedure for decreasing these particles. By using this method, we could estimate the particle generation at real time in process without stopping this equipment. Thus, both methods shown in this study could estimate the particle generation and identify the particle source with short time and high accuracy. Furthermore, they do not require long time stop of the process equipment and interrupting the production line. Therefore, these methods are concluded to be very useful and effective in LSI manufacturing process.

In a distributed-memory parallel-processing system, the overhead of data transfer among the processors is so large that it is important to reduce the data transfer. We consider the data transfer in evaluating an expression consisting of data distributed among the processors. We propose some algorithms which assign the operators in the expression to the processors so as to minimize the number or the cost of data transfers, on the condition that the data allocation to the processors is given. The basic algorithm is given at first, followed by some variations.

The Minimum Covering Run (MCR) expression used for representing binary images has been proposed [1]-[3]. The MCR expression is an adaptation from horizontal and vertical run expression. In the expression, some horizontal and vertical runs are used together for representing binary images in which total number of them is minimized. It was shown that, sets of horizontal and vertical runs representing any binary image could be viewed as partite sets of a bipartite graph, then the MCR expression of binary images was found analogously by constructing a maximum matching as well as a minimum covering in the corresponding graph. In the original algorithm, the most efficient algorithm, proposed by Hopcroft, solving the graph-theoretical problems mentioned above, associated with the Rectangular Segment Analysis (RSA) was used for finding the MCR expression. However, the original algorithm still suffers from a long processing time. In this paper, we propose two new efficient MCR algorithms that are beneficial to a practical implementation. The new algorithms are composed of two main procedures; i.e., Partial Segment Analysis (PSA) and construction of a maximum matching. It is shown in this paper that the first procedure which is directly an improvement to the RSA, appoints well a lot of representative runs of the MCR expression in regions of text and line drawing. Due to the PSA, the new algorithms reduce the number of runs used in the technique of solving the matching problem in corresponding graphs so that satisfactory processing time can be obtained. To clarify the validity of new algorithms proposed in this paper, the experimental results show the comparative performance of the original and new algorithms in terms of processing time.

An eye-contact technique using a blazed half-transparent mirror (BHM) is developed. This half-transparent mirror (HM) consists of an in-line array of many slanting micro-HMs. We fabricated a prototype system and confirmed the principle of this technique. The resolution of an image reflected by a BHM was simulated to determine how to improve the image quality and the factors degrading the resolution were clarified.

The performance of a drift-diffusion device simulator using massively parallel processors is improved by modifying the preconditioner for the iterative solver and by improving the initial guess for the Newton loop. A grid-to-processor mapping scheme is presented to implement the partitioned natural ordering preconditioner on the CM-5. A new preconditioner called the block partitioned natural ordering, which may include fill-ins, improves performance in terms of CPU time and convergence behavior on the CM-5. A multigrid discretization to implement a block Newton initial guess routine is observed to decrease the CPU time by a factor of two. Extensions of the initial guess routine show further reduction in the final fine grid linear iterations.

This paper describes Japanese spoken sentence recognition using hybrid language modeling, which combines the advantages of both syntactic and stochastic language models. As the baseline system, we adopted the HMM-LR speech recognition system, with which we have already achieved good performance for Japanese phrase recognition tasks. Several improvements have been made to this system aimed at handling continuously spoken sentences. The first improvement is HMM training with continuous utterances as well as word utterances. In previous implementations, HMMs were trained with only word utterances. Continuous utterances are included in the HMM training data because coarticulation effects are much stronger in continuous utterances. The second improvement is the development of a sentential grammar for Japanese. The sentential grammar was created by combining inter- and intra-phrase CFG grammars, which were developed separately. The third improvement is the incorporation of stochastic linguistic knowledge, which includes stochastic CFG and a bigram model of production rules. The system was evaluated using continuously spoken sentences from a conference registration task that included approximately 750 words. We attained a sentence accuracy of 83.9% in the speaker-dependent condition.

A family of new generalized LR parsing algorithms are proposed which make use of a set of ancestors tables introduced by Kipps. As Kipps's algorithm does not give us a method to extract any parsing results, his algorithm is not considered as a practical parser but as a recognizer. In this paper, we will propose two methods to extract all parse trees from a set of ancestors tables in the top vertices of a graph-structured stack. For an input sentence of length n, while the time complexity of the Tomita parser can exceed O(n3) for some context-free grammars (CFGs), the time complexity of our parser is O(n3) for any CFGs, since our algorithm is based on the Kipps's recognizer. In order to extract a parse tree from a set of ancestors tables, it takes time in order n2. Some preliminary experimental results are given to show the efficiency of our parsers over Tomita parser.