In 1963, the authors began to develop a tuning circuit (hereafter referred to as the 'circuit') consisting of an inductor, fixed capacitors and a variable capacitor. The circuit required very high accuracy and stability, and the aging influence on resonant frequency needed to be Δf/f0 0.12% for 20 years. When we started, there was no methodology available for designing such a long-term stable circuit, so we reinvestigated our previous studies concerning aging characteristics and formed a design concept. We designed the circuit by bearing in mind that an inductor was subject to natural and stress demagnetization (as indicated by disaccommodation), and assumed that a capacitor changed its characteristics linearly over a logarithmic scale of time. (This assumption was based on short-term test results derived from previous studies.) We measured the aging characteristics of the circuits at room temperature for 20 years, from 1966. The measurement results from the 20-year study revealed that the aging characteristics predicted by the design concept were reasonably accurate.

For systems in which the probability that an incorrect output is observed differs with input values, we adopt the redundant usage of n copies of identical systems which we call the n-redundant system. This paper presents a method to find the optimal redundancy of systems for minimizing the probability of dangerous errors. First, it is proved that a k-out-of-n redundancy or a mixture of two kinds of k-out-of-n redundancies minimizes the probability of D-errors under the condition that the probability of output errors including both dangerous errors and safe errors is below a specified value. Next, an algorithm is given to find the optimal series-parallel redundancy of systems by using the properties of the distance between two structure functions.

This paper presents two approaches for computing the reliability of complex networks subject to two kinds of failure, open failure and shorted failure. The reliabilities of some series-parallel networks are considered by many analysts. However a practical system is more complex. The methods given in this paper can be applied not only to a series-parallel network but also to a non-series-parallel network which is composed of non-identical and independent components subject to two kinds of failure. This paper also deals with a network subject to flow quantity constraint such as the one which is required to control j or more separate paths. For such a system it is difficult to obtain system reliability because the number of states to be considered in this system is extremely large compared to a conventional 2-state device system. In this paper we obtain the reliabilities for such systems by a combinatorial approach and by a simulation approach.

An efficient algorithm is presented for finding all solutions of piecewise-linear resistive circuits. In this algorithm, a simple sign test is performed to eliminate many linear regions that do not contain a solution. This makes the number of simultaneous linear equations to be solved much smaller. This test, in its original form, is applied to each linear region; but this is time-consuming because the number of linear regions is generally very large. In this paper, it is shown that the sign test can be applied to super-regions consisting of adjacent linear regions. Therefore, many linear regions are discarded at the same time, and the computational efficiency of the algorithm is substantially improved. The branch-and-bound method is used in applying the sign test to super-regions. Some numerical examples are given, and it is shown that all solutions are computed very rapidly. The proposed algorithm is simple, efficient, and can be easily programmed.

We propose an optical computing architecture called pure optical parall array logic system (P-OPALS) as an instance of sophisticated optical computing system. On the P-OPALS, high density images can be processed in parallel using the optical system with high resolving power. We point out problems on the way to develop the P-OPALS and propose logical foundation of the P-OPALS called single-input optical array logic (S-OAL) as a solution of those problems. Based on the proposed architecture, an experimental system of the P-OPALS is constructed by using three optical techniques: birefringent encoding, selectable discrete correlator, and birefringent decoding. To show processing capability of the P-OPALS, some basic parallel operations are demonstrated. The results obtained indicate that image consisting of 300 100 pixels can be processed in parallel on the experimental P-OPALS. Finally, we estimate potential capability of the P-OPALS.

Finding DC solutions of nonlinear networks is one of the most difficult tasks in circuit simulation, and many circuit designers experience difficulties in finding DC solutions using Newton's method. Piecewise-linear analysis has been studied to overcome this difficulty. However, efficient piecewiselinear algorithms have not been proposed for nonlinear resistive networks containing the Gummel-Poon models or the Shichman-Hodges models. In this paper, a new piecewise-linear algorithm is presented for solving nonlinear resistive networks containing these sophisticated transistor models. The basic idea of the algorithm is to exploit the special structure of the nonlinear network equations, namely, the pairwise-separability. The proposed algorithm is globally convergent and much more efficient than the conventional simplical-type piecewise-linear algorithms.

In this paper, we present some novel concepts and photonic devices for use in optical interconnects. First, we review the progress of surface emitting lasers while featuring materials and performances including thresholds, power output, RIN, linewidth, and so on. Advanced technology for aiming at spontaneous emission control, photon recycling, polarization control, wavelength tuning, integration etc. will be considered. Then we touch on some other possible devices for optical interconnects. Lastly, we discuss on lightwave subsystems applying these devices and concepts.

A transmission data format for high-speed optical parallel interconnections is proposed and a 4-channel transmitter and receiver link module operating at up to 1.2 Gb/s per channel is demonstrated. The data format features "Group Multiplexing and Coding." In this scheme, input several tens channels are multiplexed and coded in group into reduced channels, resulting in burst-mode compatible, skew-free transmission, and low power-consumption of a link module. Experiments with fabricated modules comfirm that our data coding in multichannel optical transmission is promising for use in high-speed interconnections in information and switching systems.

We propose a recognition method for HMM using a simultaneous generative histogram. Proposed method uses the correlation between two features, which is expressed by a simultaneous generative histogram. Then output probabilities of integrated HMM are conditioned by the codeword of another feature. The proposed method is applied to isolated digit word recognition to confirm its validity.

Automotive electronics technology has become extremely advanced in the regions of automotive engine control, anti-skid brake control, and others. These control systems require highly advanced control performance and high speed microprocessors which can rapidly execute interrupt processing. Automotive engine control systems are now widely utilized in cars with high speed, high power engines. At present, it is generally acknowledged that such high performance engine control for the 10,000 rpm, 12 cylinder engines requires three or more conventional microprocessors. We fabricated an engine control system prototype incorporating the data-driven processor under development, which was installed in an actual automobile. In this paper, the characteristics of the engine control program and simulation results are firstly discussed. Secondly, the structure of the engine control system prototype and the control performance applied to the actual automobile are shown. Finally, from the results of software simulation and the installation of the engine control system prototype with the data-driven processor, we conclude that a single chip data-driven microprocessor can control a high speed, high power, 10,000 rpm, 12 cylinder automobile engine.

We have developed an SIMD processor on a double-height VME board. We achieved a good balance between cost and performance by combining four identical gate-array LSIs in the processor array with a 16-bit degital signal processor (DSP), standard dynamic random-access memories (DRAMs) and other peripherals. The gate-array LSIs have 168-bit processing elements (PEs), each containing a one-bit processing block and a serial multiplier. This PE structure offers high-level bit processing capability and peak performance of 512 million operations per second (MOPS) for 8-bit multiply and accumulate operations. Effective performance of more than 300 MOPS for 8-bit array data processing is achieved by using an LSI structure tuned to the DRAM access rate, although the processing speed is reduced by the DRAM access bottleneck. The LSIs also have two unique additional hardware structures that speed up various array data processes. One is an inter-PE routing register array for supporting a transmission, rotation and memory access path. The other is a tree-structure network for propagating operations among PEs. With these cost-effective structures, the SIMD processor is expected to be widely used for two-dimensional data processing, such as image processing and pattern recognition.

The ray-tracing algorithm can synthesize very realistic images. However, the ray tracing is very time consuming. To solve this problem, a load balancing strategy using temporal coherence between images in an animation is presented for balancing computational loads among processing elements of a parallel processng system. Our parallel processing model is based on a space subdivision method for the ray-tracing algorithm. A subdivided object space is distributed among processing elements of the parallel system. To clarify the effectiveness of the load balancing strategy, we examine the system performance by computer simulation.

In this paper, we propose a polynomial time algorithm for computing the expected maximum number of vertex-disjoint s-t paths in a probabilistic basically series-parallel directed graph and a probabilistic series-parallel undirected graph with distinguished source s and sink t(st), where each edge has a mutually independent failure probability and each vertex is assumed to be failure-free.

An omnidirectional microstrip antenna using a parasitic cylinder is presented. A rectangular patch is formed on a dielectric substrate and it's completely covered with an aluminum cylinder which is somewhat shorter than a half of free space wavelength. Under such configuration the aluminum cylinder works as a parasitic element. This antenna can provides uniform omnidirectional radiation patterns and a broad frequency bandwidth. In this paper an experimental method for designing such an element is described. Measured input impedance characteristics, current distribution around the surface of the cylinder and patterns are also shown. By properly adjusting the coupling intensity between the patch and the parasitic cylinder a broad bandwidth antenna element can be realized. Some methods to adjust the coupling intensity are shown. A wide bandwidth element up to 14% for VSWR1.5 is obtained. Arranging many patches lengthways on a substrate and placing metallic cylinders around each patches, we can realize a high-gain and broad bandwidth collinear antenna.

This paper describes an error-correcting parser (ec-parser) for context-free languages that is an extension of the Leiss's parser. Since the ec-parser uses precomputed informations and a pruning technique by lookahead, the ec-parser is always faster than the Lyon's parser. Several examples are shown.

The development of highly accurate and durable control system is becoming a must for todays high performance automobiles. For example, it is necessary to up-grade todays materials and methods creating more sensitive sensors, higher speed processors and more accurate actuators, while also being more durable. Thus, the development of a CMOS time-to-digital converter LSI with half-nanosecond resolution, which controls only pulse signals was achieved by employing 1.5 µm CMOS technology. The new signal detecting circuit, 1.1 mm2 in size, converts time to numerical values over a wide measurement range (13 bits). The compact digital circuit employs a newly developed "ring gate delay system". Within the LSI the fully digital circuit is highly durable. This allows it to be utilized even under severe conditions (for example an operating ambient temperature of 130). In order to measure time accurately, a method of correcting the variation of measurement time data employing a real-time conversion fully digital circuit is described. This method allows for fully automatic correction with a microcomputer, so no manual adjustment is required. In addition to sensor circuit applications, the LSI has great potential for Application Specific Integrated Circuit, (ASIC) such as a function cell with is a completely new method of measuring time.

This paper proposes a reconfigurable parallel processor based on a two-dimensional linear celular automaton model. The processor based on the model can be reconfigured quickly by utilizing the characteristics of the automaton used for its model. Moreover, the processor has short data path length between processing elements compared with the length of the processor based on one-dimensional linear cellular automaton model which has been already discussed. The processing elements of the processor based on the two-dimensional linear cellular automaton model are regarded as cells and the operational states of the processor are treated as the states of the automaton. When faults are detected, the processor can be reconfigured by changing its state under the state transition function of the processor determined by the weighting function of the automaton model. The processor can be reconfigured within a clock period required for making a state transition. This processor is extremely effective for real-time data processing systems required high reliability.

For analyzing the transient electromagnetic fields caused by electrostatic discharge (ESD), a new ESD model is presented here. Numerical calculation is also given to explain the distinctive phenomenon being well-recognized in the ESD event.

We deal with a new type ceramic emitter which is used in a cleanroom ionizer system and is composed of a needle-shaped silicon and a rod-shaped silicon carbide ceramics. The discharge test was carried out to investigate the particle generation from the emitter and the degradation of the emitter. As a result, it was found that the ceramic emitter had practically higher performance than a conventional tungsten emitter.

The emerging discipline of responsive systems demands fault-tolerant and real-time performance in uniprocessor, parallel, and distributed computing environments. The new proposal for responsiveness measure is presented, followed by an introduction of a model for responsive computing. The model, called CONCORDS (CONsensus/COmputation for Responsive Distributed Systems), is based on the integration of various forms of consensus and computation (progress or recovery). The consensus tasks include clock synchronization, diagnosis, checkpointing scheduling and resource allocation.