In these days, many dynamically reconfigurable architectures have been introduced to fill the gap between ASICs and software-programmed processors such as GPPs and DSPs. These reconfigurable architectures have shown to achieve higher performance compared to software-programmed processors. However, reconfigurable architectures suffer from a significant reconfiguration overhead and a speedup limitation. By reducing the reconfiguration overhead, the overall performance of reconfigurable architectures can be improved. Therefore, we will describe temporal partitioning, which are able to amortize the reconfiguration overhead at synthesis phase or compilation time. Our temporal partitioning methodology splits a configuration context into temporal partitions to amortize reconfiguration overhead. And then, we will present benchmark results to demonstrate the effectiveness of our methodology.

FeedForward (FF-) Blind Source Separation (BSS) systems have some degree of freedom in the solution space. Therefore, signal distortion is likely to occur. First, a criterion for the signal distortion is discussed. Properties of conventional methods proposed to suppress the signal distortion are analyzed. Next, a general condition for complete separation and distortion-free is derived for multi-channel FF-BSS systems. This condition is incorporated in learning algorithms as a distortion-free constraint. Computer simulations using speech signals and stationary colored signals are performed for the conventional methods and for the new learning algorithms employing the proposed distortion-free constraint. The proposed method can well suppress signal distortion, while maintaining a high source separation performance.

This paper addresses parallel prefix adder synthesis which targets area minimization under given bitwise timing constraints. This problem is treated as a problem to synthesize prefix graphs which represent global structures of parallel prefix adders at technology-independent level, and a two-folded algorithm to minimize area of prefix graphs is proposed. The first process is dynamic programming based area minimization (DPAM), which focuses on a specific subset of prefix graphs and finds an exact minimum solution for the subset by dynamic programming. The subset is defined by imposing some restrictions on structures of prefix graphs. By utilizing these restrictions, DPAM can find the minimum solutions efficiently for practical bit width. The second process is area reduction with re-structuring (ARRS), which removes the imposed restrictions on structures, and restructures the result of DPAM for further area reduction while satisfying timing constraints. Experimental results show that smaller area can be achieved compared to existing methods both at prefix graph level and at gate level.

Impulse Radio (IR)-Ultra Wideband (UWB) enables accurate ranging due to very short duration pulses. Therefore, UWB may provide accurate positioning capability. In order to relax the complexity in circuit implementation, UWB system with low resolution analog digital converters (ADCs) has been investigated. In this paper, the accuracy of UWB positioning with comparators is investigated through experiment. The accuracy of positioning with comparators is compared to that with 8 [bit] ADCs, and effectiveness of the system with the comparators is confirmed within the area of 1.81.8 [m].

A blind joint parametric channel estimation and non-coherent data detection algorithm is proposed for the downlink of an orthogonal-frequency-division-multiplexing code-division-multiple-access (OFDM-CDMA) system with multiple-input-multiple-output (MIMO) antenna arrays. To reduce the computational complexity, we first develop a tree-structured algorithm to estimate high dimensional parameters predominantly describing the involved multipath channels by employing several stages of low dimensional parameter estimation algorithms. In the tree structure, to exploit the space-time distribution of the receive multipath signals, spatial beamformers and spectral filters are adopted for clustered-multipath grouping and path isolation. In conjunction with the multiple access interference (MAI) suppression techniques, the proposed tree architecture algorithm jointly estimates the direction of arrivals, propagation delays, carrier frequency offsets and fading amplitudes of the downlink wireless channels in a MIMO OFDM-CDMA system. With the outputs of the tree architecture, the signals of interest can then be naturally detected with a path-wise maximum ratio combining scheme.

To describe joint time- and frequency-selective (doubly-selective) channels in mobile broadband wireless communications, we propose to use the finite parameter model based on the same Bessel functions for each tap (Bessel model). An expression of channel estimation mean squared error (MSE) based on the finite parameter models in Orthogonal Frequency Division Multiplexing (OFDM) systems is derived. Then, our Bessel model is compared with commonly used finite parameter models in terms of the channel estimation MSE. Even if the channel taps have different channel correlations and some of the taps do not coincide with the Bessel function, the channel estimation MSE of the Bessel model is shown to be comparable or outperform existing models as validated by Monte-Carlo simulations over an ensemble of channels in typical urban and suburban environments.

A novel low-complexity iterative receiver for coded multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) systems is proposed in this letter. The iterative receiver uses the parallel interference cancellation (PIC)-maximum ratio combining (MRC) detector for MIMO-OFDM detection, which is a popular alternative to the minimum mean square error (MMSE) detector due to its lower computational complexity. However, we have found that the conventional PIC-MRC detector tends to underestimate the magnitude of its output log likelihood ratios (LLRs). Based on this discovery, we propose to multiply these LLRs by a constant factor, which is optimized according to the extrinsic information transfer (EXIT) chart of the soft-in soft-out (SISO) detector. Simulation results show that the proposed scheme significantly improves the performance of the PIC-MRC-based receiver with little additional cost in computational complexity, allowing it to closely approach the performance of receiver using the much more complex MMSE detector.

In recent years, algorithms based on Computer Algebra ([1]-[3]) have been introduced into a range of control design problems because of the capacity to handle unknown parameters as indeterminates. This feature of algorithms in Computer Algebra reduces the costs of computer simulation and the trial and error process involved, enabling us to design and analyze systems more theoretically with the behavior of given parameters. In this paper, we apply Computer Algebra algorithms to H∞ control theory, representing one of the most successful achievements in post-modern control theory. More specifically, we consider the H∞ norm minimization problem using a state feedback controller. This problem can be formulated as follows: Suppose that we are given a plant described by the linear differential equation = Ax + B1w + B2u, z = Cx + Du, where A,B1,B2,C,D are matrices whose entries are polynomial in an unknown parameter k. We apply a state feedback controller u = -F x to the plant, where F is a design parameter, and obtain the system = (A - B2F)x + B1w, z =(C - DF)x. Our task is to compute the minimum H∞ norm of the transfer function G(s)(=(C - DF)(sI - A + B2F)-1B1) from w to z achieved using a static feedback controller u = -Fx, where F is a constant matrix. In the H∞ control theory, it is only possible to check if there is a controller such that ||G(s)||∞ < γ is satisfied for a given number γ, where ||G(s)||∞ denotes the H∞ norm of the transfer function G(s). Thus, a typical procedure to solve the H∞ optimal problem would involve a bisection method, which cannot be applied to plants with parameters. In this paper, we present a new method of solving the H∞ norm minimization problem that can be applied to plants with parameters. This method utilizes QE (Quantifier Elimination) and a variable elimination technique in Computer Algebra, and expresses the minimum of the H∞ norm as a root of a bivariate polynomial. We also present a numerical example to illustrate each step of the algorithm.

The computational complexity of the optimum maximum likelihood detector (OMLD) does not allow its utility for multi-user detection (MUD) in code division multiple access (CDMA) systems. As proposed in this letter, particle swarm optimization (PSO) with soft decision offers a much more efficient option with few parameters to be adjusted, flexibility to implement, that gives a much faster convergence compared to OMLD. It outperforms the conventional detector, the genetic algorithm approach and the standard suboptimal detectors considered in the literature.

We demonstrate a novel display structure for color electronic paper for the first time. Fully transparent amorphous oxide TFT array is directly deposited onto color filter array and combined with E Ink Imaging Film. Taking advantage of the transparent property of the oxide TFT, the color filter and TFT array are positioned at the viewing side of the display. This novel "Front Drive" display structure facilitates the alignment of the color filter and TFT dramatically.

A comparison is made between the performance of the MMIC matrix and distributed amplifiers. It has been shown that based on the analytical formulations, in most typical cases a cascaded dual stage distributed amplifier has more gain than that of a two-tier matrix amplifier with the same number of transistors; however the difference is not significant. Results of the analytical approach are then compared with the simulated and the measured results and a good agreement between the results has been obtained. Then other scattering parameters of the matrix and distributed amplifiers have been compared.

A new method is presented in order to improve the transient response of distributed amplifiers. The method is based on fitting the parameters of the distributed amplifier to those of a predesigned lowpass filter. Analytical expressions are derived to show the performance of the new structure. Three distributed amplifiers are designed based on the proposed method and it has been shown that the new method can significantly improve the transient response of the amplifier. It has been shown that the new method can improve the other characteristics of the distributed amplifier too. The effects of parasitic and lossy elements has also been considered and it has been shown that such effects doesn't violate the generality of the proposed theory.

This study presents a partition decoding algorithm for an (mN, mK) binary image of an (N, K) Reed Solomon code over GF(2m). A proposed partition decoding algorithm includes several steps. Firstly we compute m's segmental reliability values of a received subvector of length N and determine which one with the least segmental reliability value. A permutation is performed on a binary generator matrix of an RS code and a received vector, which are then partitioned into two submatrices and two subvectors. The first subvector of length N(m-1) associate with the first submatrix and the second subvector with the least segmental reliability value relates to the second submatrix. Secondly, an MLD algorithm based on the first submatrix is employed to decode the first subvector. Thirdly, an MLD algorithm based on a BCH generator matrix is employed to decode the second subvector. A codeword is finally outputted after performing the inverse permutation on a concatenation of code vectors decoded from these two decoding. The error coefficient and minimum Hamming distance of the code sequences generated in the first submatrix are fewer than those of a corresponding binary image. Simulation results show that at low and medium SNRs, the effect of error coefficient becomes more significant than that of minimum Hamming distance. Minimum Hamming distances and error coefficients of code sequences generated in the first submatrices and their corresponding binary images have been explored in this work. For (60,36,7)RS(b), (155,125,7)RS(b), (155,105,11)RS(b) and (889, 847,7))RS(b) being binary images of (15,9,7)RS, (31,25,7)RS, (31,21,11)RS and (127,121,7)RS codes respectively, with BPSK signaling over AWGN channels, the decoding performances of proposed partition decoding algorithm are a little poorer than those of MLD [10] by 1.0 to 1.4 dB at BER 10-5, but better than those of GMD decoding by [1] 0.8 to 1.1 dB. For SNR of 5 dB, proposed partition decoding algorithm only takes 50% to 60% amount of bit operations of an MLD [10]. Under a constraint of decoding complexity, proposed partition decoding algorithm may be a solution to decode binary images of long RS codes, which provides superior performance to GMD decoding with much lower complexity than an MLD.

In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consumption of check operation module is reduced by 40%, while achieving a negligible performance loss compared with the general min-sum algorithm. To reduce the power dissipation of the decoder, we also proposed a power-saved strategy, according to which the message evolution halts as the parity-check condition is satisfied. This strategy reduces more than 50% power under good channel condition. The synthesis result in 0.18 µm CMOS technology shows our decoder based on (648,540) irregular LDPC code of WLAN (802.11n) protocol achieves 810 [Mbps] throughput with 283 [mW] power consumption.

Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed.

Particle swarm optimization (PSO), inspired by social psychology principles and evolutionary computations, has been successfully applied to a wide range of continuous optimization problems. However, research on discrete problems has been done not much even though discrete binary version of PSO (BPSO) was introduced by Kennedy and Eberhart in 1997. In this paper, we propose a modified BPSO algorithm, which escapes from a local optimum by employing a bit change mutation. The proposed algorithm was tested on De jong's suite and its results show that BPSO with the proposed mutation outperforms the original BPSO.

In this paper, we have systematically investigated parasitic effects due to the gate and source-drain engineering in multi-gate transistors. The potential impact of high-K dielectrics on multi-gate MOSFETs (MuGFETs), such as FinFET, is evaluated through 2D and 3D device simulations over a wide range of proposed dielectric values. It is observed that introduction of high-K dielectrics will significantly degrade the short channel effects (SCEs), however a combination of oxide and high-K stack can effectively control this degradation. The degradation is mainly due to the increase in the internal fringe capacitance coupled with the decrease in gate-channel capacitance. From the circuit perspective, an optimum K value has been identified through mixed mode simulations. Further, as a part of this work, the importance of optimization of the shape of the spacer region is highlighted through full 3D simulations.

This paper presents media processor architectures for automotive applications. Media processing applications with their requirements for LSI implementations are first described for vision based driver assistance as well as graphical user interface for car navigation using 3D graphics. Then, parallel processing architectures for vision and graphics in these applications are reviewed with their performance and cost. After that, future trends of automotive media processing such as integration of vision and 3D graphics functions are shown with their applications and the required performance. Moreover, parallel processing architectures are discussed for the integration of vision and graphics. Finally, an prospect of a next-generation media processing LSI for automotives is provided.

This paper describes logic and analog test schemes that improve the testability of a pixel-parallel fingerprint identification circuit. The pixel contains a processing circuit and a capacitive fingerprint sensor circuit. For the logic test, we propose a test method using a pseudo scan circuit to check the processing circuits of all pixels simultaneously. In the analog test, the sensor circuit employs dummy capacitance to mimic the state of a finger touching the chip. This enables an evaluation of the sensitivity of all sensor circuits on logical LSI tester without touching the chip with a finger. To check the effectiveness of the schemes, we applied them to a pixel array in a fingerprint identification LSI. The pseudo scan circuit achieved a 100% failure-detection rate for the processing circuit. The analog test determines that the sensitivities of the sensor circuit in all pixels are in the proper range. The results of the tests confirmed that the proposed schemes can completely detect defects in the circuits. Thus, the schemes will pave the way to logic and analog tests of chips integrating highly functional devices stacked on a LSI.

In this paper, we propose an accurate and scalable S-parameter de-embedding method for RF/microwave on-wafer characterization of silicon MOSFETs. Based on cascade configurations, this method utilizes planar open, short, and thru standards to estimate the effects of surrounding parasitic networks on a MOS transistor. The bulk-shielded open and short standards are used to simulate and de-embed the probe-pad parasitics. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate and drain terminals of the MOSFET. To further eliminate the parasitics of dangling leg in source terminal of the MOSFET, we also introduce the microwave and multi-port network analysis to accomplish the two-port-to-three-port transformation for S-parameters. The MOSFET and its corresponding de-embedding standards were fabricated in a standard CMOS process and characterized up to 40 GHz. The scalability of the open, short, and thru standards is demonstrated and the performance of the proposed de-embedding procedure is validated by comparison with several de-embedding techniques.