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3041-3060hit(3318hit)

  • A New Wide Applicable Mobility Model for Device Simulation Taking Physics-Based Carrier Screening Effects into Account

    Koichi FUKUDA  Kenji NISHI  

     
    PAPER

      Vol:
    E78-C No:3
      Page(s):
    281-287

    Carrier mobility is one of the most fundamental parameters in semiconductor device modeling, and many mobility models have already been reported. Especially for numerical device simulators, many local models which are functions of impurity concentration and electric field at each local point have been studied. However, concerning their dependence on impurity concentration including carrier screening effects, these models suffer parameter fitting procedure because of their empirical formulation. In such models, carrier screening effects to the Coulomb potential of ionized impurity are not sufficiently considered, although we can find some models which treat the effects as only a small perturbation term. According to the simple theory of Brooks and Herring, carrier screening effects should be included in strong combination with impurity concentration terms and cannot be treated as additional perturbations. Although Brooks-Herring theory is successful, it also suffers from overestimation of the mobility values at concentration higher than 1018 cm-3 which causes some other complicated phenomena. Therefore there have been no models which directly use Brooks-Herring formula. But it is true that such screening effects should be considered when carrier concentration differs from impurity concentration as in the inversion layers of MOSFETs. We have developed a new mobility model for its dependence of impurity and carrier concentration based on the theory of Brooks-Herring. Brooks-Herring theory is based on simple physics of screened Coulomb potential, and therefore makes the model to include effects of free carriers without an artifitial formula. For high doping regime, an additional term has been introduced in Brooks-Herring formula to correct the high doping effects. Except for this term, the model should be most appropriate for including the carrier screening effects upto the concentration of 1018 cm-3. The new model is implimented in a device simulator, and is applied to the evaluation of MOSFETs especially for the universal curves of inversion layer mobility. Moreoever, the applications to the depletion-type MOSFET confirm the validity of the screening effects. The purpose of this paper is to propose the new mobility model and to show its validity through these applications to MOSFETs.

  • Parallel Algorithms for Refutation Tree Problem on Formal Graph Systems

    Tomoyuki UCHIDA  Takayoshi SHOUDAI  Satoru MIYANO  

     
    PAPER-Algorithm and Computational Complexity

      Vol:
    E78-D No:2
      Page(s):
    99-112

    We define a new framework for rewriting graphs, called a formal graph system (FGS), which is a logic program having hypergraphs instead of terms in first-order logic. We first prove that a class of graphs is generated by a hyperedge replacement grammar if and only if it is defined by an FGS of a special form called a regular FGS. In the same way as logic programs, we can define a refutation tree for an FGS. The classes of TTSP graphs and outerplanar graphs are definable by regular FGSs. Then, we consider the problem of constructing a refutation tree of a graph for these FGSs. For the FGS defining TTSP graphs, we present a refutation tree algorithm of O(log2nlogm) time with O(nm) processors on an EREW PRAM. For the FGS defining outerplanar graphs, we show that the refutation tree problem can be solved in O(log2n) time with O(nm) processors on an EREW PRAM. Here, n and m are the numbers of vertices and edges of an input graph, respectively.

  • Defect-Tolerant WSI File Memory System Using Address Permutation for Spare Allocation

    Eiji FUJIWARA  Masaharu TANAKA  

     
    PAPER-Fault Tolerant Computing

      Vol:
    E78-D No:2
      Page(s):
    130-137

    This paper proposes a large capacity high-speed file memory system implemented with wafer scale RAM which adopts a novel defect-tolerant technique. Based on set-associative mapping, the defective memory blocks on the wafer are repaired by switching with the spare memory blocks. In order to repair the clustered defective blocks, these are permuted logically with other blocks by adding some constant value to the input block addresses. The defective blocks remaining even after applying the above two methods are repaired by using error control codes which correct soft errors induced by alpha particles in an on-line operation as well as hard errors induced by the remaining defective blocks. By using the proposed technique, this paper demonstrates a large capacity high-speed WSI file memory system implemented with high fabrication yield and low redundancy rate.

  • Adaptive Density Pulse Excitation for Low Bit Rate Speech Coding

    Masami AKAMINE  Kimio MISEKI  

     
    PAPER-Digital Signal Processing

      Vol:
    E78-A No:2
      Page(s):
    199-207

    An excitation signal for a synthesis filter plays an important role in producing high quality speech at a low bit rate. This paper presents a new efficient excitation model, Adaptive Density Pulse (ADP) , for low bit-rate speech coding. This ADP is a pulse train whose density (spacing interval) is constant within a subframe but can be varied subframe by subframe. First, the ADP excitation signal is defined. A procedure for finding the optimal ADP excitation is presented. Some results on investigating the effects of the ADP parameters on the synthesized speech quality are discussed. ADP excitation is introduced to the CELP (Code Excited Linear Prediction) coding method to improve speech quality at bit rates around 4 kbps. A CELP coder with an ADP (ADP-CELP) is described. ADP excitation makes it possible for the CELP coder to follow transient portions of speech signals. Also ADP excitation can reduce computational complexity in selecting the best excitation from a codebook, which has been the primary drawback of CELP. The number of multiplications can be reduced to the order of 1/D2 by utilizing the sparseness of ADP excitation, where D is the pulse interval. The authors evaluated the speech quality of a 4 kbps ADP-CELP coder by computer simulation. ADP excitation improved the performance of conventional CELP in segmental SNR.

  • Design of TCM Signals for Class-A Impulsive Noise Environment

    Shinichi MIYAMOTO  Masaaki KATAYAMA  Norihiko MORINAGA  

     
    PAPER

      Vol:
    E78-B No:2
      Page(s):
    253-259

    In this paper, a design of TCM signals for Middleton's class-A impulsive noise environment is investigated. The error event characteristics under the impulsive noise is investigated, and it is shown that the length of the signal sequence is more important than Euclidean distance between the signal sequences. Following this fact, we introduce the shortest error event path length as a measure of the signal design. In order to make this value large, increasing of states of convolutional codes is employed, and the performance improvement achieved by this method is evaluated. Numerical results show the great improvement of the error performance and conclude that the shortest error event path length is a good measure in the design of TCM signals under impulsive noise environment. Moreover, the capacity of class-A impulsive noise channel is evaluated, and the required signal sets expansion rates to obtain the achievable coding gain is discussed.

  • FM Laser Operation of a Ti:Sapphire Laser

    Akihiro MORIMOTO  Tadao OKIMOTO  Akira SOGA  Tetsuro KOBAYASHI  

     
    LETTER

      Vol:
    E78-C No:1
      Page(s):
    88-90

    FM laser operation of a Ti:sapphire laser is studied experimentally for the first time with an internal phase modulator. We obtained extremely wide FM sidebands of 8 THz width whose phase modulation index was 25,000 rad at a modulation frequency of 160 MHz.

  • Long-Distance Soliton Transmission up to 20 Gbit/s Using Alternating-Amplitude Solitons and Optical TDM

    Masatoshi SUZUKI  Noboru EDAGAWA  Hidenori TAGA  Hideaki TANAKA  Shu YAMAMOTO  Yukitoshi TAKAHASHI  Shigeyuki AKIBA  

     
    INVITED PAPER

      Vol:
    E78-C No:1
      Page(s):
    12-21

    Feasibility of 20 Gbit/s single channel transoceanic soliton transmission systems with a simple EDFA repeaters configuration has been studied. Both a simple and versatile soliton pulse generator and a polarization insensitive optical demultiplexer, which can provide a almost square shape optical gate with duration of full bit time period, have been proposed and demonstrated by using sinusoidally modulated electroabsorption modulators. The optical time-division multiplexing/demultiplexing scheme using the optical demultiplexer results in drastic improvement of bit error rate characteristics. We have experimentally confirmed that the use of alternating-amplitude solitons is an efficient way to mitigate not only soliton-soliton interaction but also Gordon-Haus timing jitter constraints in multi-ten Gbit/s soliton transmission. Timing jitter reduction using relatively wide band optical filter bas been investigated in 20 Gbit/s loop experiments and single-carrier, single-polarization 20 Gbit/s soliton data transmission over 11500 km with bit error rate of below 10-9 has been experimentally demonstrated, using the modulator-based soliton source, the optical demultiplexer, the alternation-amplitude solitons, and wide-band optical filters. Obtained 230 Tbit/skm transmission capacity shows the feasibility of 20 Gbit/s single channel soliton transoceanic systems using fully practical technologies.

  • Polarization Dependence of Soliton Interactions in Femtosecond Soliton Transmission

    Tomoki SUGAWA  Kenji KUROKAWA  Hirokazu KUBOTA  Masataka NAKAZAWA  

     
    PAPER

      Vol:
    E78-C No:1
      Page(s):
    28-37

    The polarization dependence of femtosecond soliton-soliton interactions is investigated in detail. When the polarization direction of two solitons is orthogonal, the soliton interaction can be reduced in comparison to that for parallel polarization. The soliton self-frequency shift (SSFS) is still observed even in the orthogonal condition, but the quantity of the SSFS is much smaller than in the parallel condition. A stronger soliton interaction is observed between two solitons in an in-phase condition, than in an out-of-phase condition. The largest SSFS occurs in-phase with parallel polarization. The polarization dependence of femtosecond soliton interaction in a distributed erbium-doped fiber amplifier (DEDFA) is also investigated. It is shown that when the optical gain of the DEDFA is given adiabatically, the input pulse separation at which the first soliton occurs is less with orthogonal polarization. This is because the soliton pulse width is reduced due to the adiabatic soliton narrowing caused by the optical amplification.

  • On the Number of Negations Needed to Compute Parity Functions

    Tetsuro NISHINO  Jaikumar RADHAKRISHNAN  

     
    LETTER-Algorithm and Computational Complexity

      Vol:
    E78-D No:1
      Page(s):
    90-91

    We exactly determine the number of negations needed to compute the parity functions and the complement of the parity functions. We show that with k NOT gates, parity can be computed on at most 2k+11 variables, and parity complement on at most 2k+12 variables. The two bounds are shown to be tight.

  • Unification-Failure Filter for Natural Language

    Alfredo M. MAEDA  Hideto TOMABECHI  Jun-ichi AOE  

     
    PAPER-Software Systems

      Vol:
    E78-D No:1
      Page(s):
    19-26

    Graph unification is doubtlessly the most expensive process in unification-based grammar parsing since it takes the vast majority of the total parsing time of natural language sentences. A parsing time overload in unification consists in that, in general, no less than 60% of the graph unifications performed actually fail. Thus one way to achieve unification time speed-up is focusing on an efficient, fast way to deal with such unification failures. In this paper, a process, prior to unification itself, capable of filtering or stopping a considerably high percentage of graphs that would fail unification is proposed. This unification-filtering process consists of comparison of signatures that correspond to each one of the graphs to be unified. Unification-filter (hereafter UF) is capable of stopping around 87% of the non-unifiable graphs before unification itself takes place. UF takes significantly less time to detect graphs that do not unify and discard them than it would take to unification to fail the attempt to unify the same graphs. As a result of using UF, unification is performed in an around 71% of the time for the fastest known unification algorithm.

  • Complexity of Finding Alphabet Indexing

    Shinichi SHIMOZONO  Satoru MIYANO  

     
    PAPER-Algorithm and Computational Complexity

      Vol:
    E78-D No:1
      Page(s):
    13-18

    For two finite disjoint sets P and Q of strings over an alphabet Σ, an alphabet indexing for P, Q by an indexing alphabet Γ with |Γ||Σ| is a mapping :ΣΓ satisfying (P)(Q), where :Σ*Γ* is the homomorphism derived from . We defined this notion through experiments of knowledge acquisition from amino acid sequences of proteins by learning algorithms. This paper analyzes the complexity of finding an alphabet indexing. We first show that the problem is NP-complete. Then we give a local search algorithm for this problem and show a result on PLS-completeness.

  • Short Optical Pulse Generation and Modulation by a Multi-Section MQW Modulator/DFB Laser Integrated Light Source

    Koichi WAKITA  Kenji SATO  Isamu KOTAKA  Yasuhiro KONDO  Mitsuo YAMAMOTO  

     
    PAPER

      Vol:
    E78-C No:1
      Page(s):
    50-54

    A new device consisting of an optical pulse generation section and pulse coding section monolithically integrated on a single-chip has been developed. The pulse generation section consists of a multiple quantum well (MQW) electroabsorption modulator integrated with an MQW DFB laser. The modulator operates at large-signal modulation and low voltage (from 2 to 3-V DC bias with a 3.2-V peak-to-peak RF signal). The second modulator is operated independently as a pulse encoder. An approximately transform-limited optical pulse train, whose full width at half maximum (FWHM) in the time domain is less than 17-ps and spectral FWHM is 28-GHz, is obtained with a repetition frequency of 10-GHz. Compressive strain is introduced in both InGaAsP quantum wells in order to obtain efficient device characteristics. These include a low threshold current (18-mA) for the laser, and low driving voltage (30-dB for 3-V swing) and high-speed operation (over 12-GHz for a 3-dB bandwidth) for the modulators. Demonstrations show that this new device generates short optical pulses encoded by a pseudo-random signal at a rate of 10 Gbit/s. This is the first time 10 Gbit/s modulation has been achieved with a multi-section electroabsorption modulator/DFB laser integrated light source. This monolithic device is expected to be applied to optical soliton transmitters.

  • Network Management System Using Distributed Computing

    Tamiya OCHIAI  

     
    PAPER

      Vol:
    E78-B No:1
      Page(s):
    54-60

    This paper proposes a suitable distributed computing model as the basis for building a network management system. Author has been studying a distributed reactive model, called Meta for this purpose at Cornell University. Effectiveness using Meta is to provide high level program interface for developing network management system, and programmers can achieve network management system with coding small amount of programs. It also realizes easy additions and modifications for network management application programs. To confirm the effectiveness of the proposal, the author has utilized Meta to implement an experimental network management system. The experimental system provides high level interfaces for monitoring and controlling network components. It also supports reliable communication over distributed nodes. Preliminary evaluation of the system shows that critical network management applications are provided within an appropriate response time for all applications provided by SNMP, with small development cost and easy system modification.

  • The Effect of Internal Parasitic Capacitances in Series-Connected MOS Structure

    Sang Heon LEE  Song Bai PARK  Kyu Ho PARK  

     
    LETTER-VLSI Design Technology

      Vol:
    E78-A No:1
      Page(s):
    142-145

    A simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances.

  • Information Leakage Measurement in a Distributed Computation Protocol

    Shin-ichi KAWAMURA  

     
    PAPER

      Vol:
    E78-A No:1
      Page(s):
    59-66

    This paper deals with the information leakage measurement in a distributed computation protocol called SASC. The SASC protocol is a kind of two-party protocol between a client and a server. The computation for RSA cryptosystem is the target of this paper. This paper shows that a secure RSA-SASC protocol proposed recently could be changed to be insecure if the client which has secret information were to complain about the computation result. This paper first clarifies how to measure the information amount which leaks through the protocol. It, then, shows an attack procedure to make use of the client's complaint. Effectiveness of the attack procedure is measured by the information theoretic measure. By using the same measure, it is shown that some attacks do not work to derive the client's secret. It is also shown that a practical countermeasure to limit the number of incorrect computation allowed is effctive to limit the leakage of the secret information to some reasonable extent.

  • Two Algorithms for Modular Exponentiation Using Nonstandard Arithmetics

    Vassil DIMITROV  Todor COOKLEV  

     
    LETTER

      Vol:
    E78-A No:1
      Page(s):
    82-87

    Two new algorithms for performing modular exponentiation are suggested. Nonstandard number systems are used. The first algorithm is based on the representing the exponent as a sum of generalized Fibonacci numbers. This representation is known as Zeckendorf representation. When precomputing is allowed the resulting algorithm is more efficient than the classical binary algorithm, but requires more memory. The second algorithm is based on a new number system, which is called hybrid binary-ternary number system (HBTNS). The properties of the HBTNS are investigated. With or without precomputing the resulting algorithm for modular exponentiation is superior to the classical binary algorithm. A conjecture is made that if more bases are used asymptotically optimal algorithm can be obtained. Comparisons are made and directions for future research are given.

  • A Parallel BBD Matrix Solution for MIMD Parallel Circuit Simulation

    Tetsuro KAGE  Junichi NIITSUMA  

     
    PAPER-Computer Aided Design (CAD)

      Vol:
    E78-A No:1
      Page(s):
    88-93

    We developed a parallel bordered-block-diagonal (BBD) matrix solution for parallel circuit simulation. In parallel circuit sumulation on a MIMD parallel computer, a circuit is partitioned into as many subcircuits as the processors of a parallel computer. Circuit partition produce a BBD matrix. In parallel BBD matrix solution, diagonal blocks are easily solved separately in each processor. It is difficult, however, to solve the interconnection (IC) submatrix of a BBD matrix effectively in parallel. To make matters worse, the more a circuit is partitioned into subcircuits for highly parallel circuit simulation, the larger the size of an IC submatrix becomes. From an examination, we found that an IC submatrix is more dense (about 30% of all entries are non-zeros) than a normal circuit matrix, and the non-zeros per row in an IC submatrix are almost constant with the number of subcircuits. To attain high-speed circuit simulation, we devised a data structure for BBD matrix processing and an approach to parallel BBD matrix solution. Our approach solves the IC submatrix in a BBD matrix as well as the diagonal blocks in parallel using all processors. In this approach, we allocate an IC submatrix in block-wise order rather than in dot-wise order onto all processors. Thus, we balance the processor perfomance with the communication capacity of a parallel computer system. When we changed the block size of IC submatrix allocation from dot-wise order to 88 block-wise order, the 88 block-wise order allocation almost halved the matrix solution time. The parallel simulation of a sample circuit with 3277 transistors was 16.6 times faster than a single processor when we used 49 processors.

  • LSI Neural Chip of Pulse-Output Network with Programmable Synapse

    Shigeo SATO  Manabu YUMINE  Takayuki YAMA  Junichi MUROTA  Koji NAKAJIMA  Yasuji SAWADA  

     
    PAPER-Integrated Electronics

      Vol:
    E78-C No:1
      Page(s):
    94-100

    We have fabricated a microchip of a neural circuit with pulse representation. The neuron output is a voltage pulse train. The synapse is a constant current source whose output is proportional to the duty ratio of neuron output. Membrane potential is charged by collection of synaptic currents through a RC circuit, providing an analog operation similar to the biological neural system. We use a 4-bit SRAM as the memory for synaptic weights. The expected I/O characteristics of the neurons and the synapses were measured experimentally. We have also demonstrated the capability of network operation with the use of synaptic weights, for solving the A/D conversion problem.

  • On the Negation-Limited Circuit Complexity of Clique Functions

    Tetsuro NISHINO  Keisuke TANAKA  

     
    LETTER-Algorithm and Computational Complexity

      Vol:
    E78-D No:1
      Page(s):
    86-89

    A negation-limited circuit is a combinational circuit which includes at most [log(n1)] NOT gates. We show a relationship between the size of negation-limited circuits computing clique functions and the number of NOT gates in the circuits.

  • Communicative Characteristics of Small Group Teleconferences in Virtual Environments

    Atsuya YOSHIDA  Jun KAKUTA  

     
    PAPER

      Vol:
    E77-D No:12
      Page(s):
    1385-1389

    When we design a human interface of a computer-mediated communication (CMC) system, it is important to take a socio-behavioral approach for understanding the nature of the human communication. From this point of view, we conducted experimental observations and post-experimental questionnaires to investigate communicative characteristics in a teleconference using Fujitsu Habitat" visual telecommunication software. We experimentally held the following three kinds of small-group conferences consisting of five geographically distributed participants: (a) teleconference using a visual telecommunication system (Fujitsu Habitat"), (b) teleconference using a real-time keyboard telecommunication system of NIFTY-Serve and (c) live face to face physical conference. Analyses were made on (1) effects of the media on utterance behaviors of conference members, and (2) satisfaction of conference members with communicative functions of the media. Satisfaction was measured by a seven-level rating scale. We found that participants in a telconference held by using Habitat showed significant differences in contents of utterances and the rating of satisfaction with nine communicative functions compared with those of conferences held by using a real-time keyboard telecommunication system and a live face-to-face conference. These results suggest some features that could facilitate multi-participant on-line electronic conferences and conversations.

3041-3060hit(3318hit)