Test pattern generation is getting much harder as the circuit size becomes larger. One problem is that it tends to take much time and another one is that it is difficult to detect redundant faults. Aiming to cope with these problem, an enhanced unique sensitization technique is proposed in this paper. This powerful global implication reduces the number of backtracks with reasonable computational time. And a fast test pattern generator featuring this unique sensitization demonstrates its performance using large benchmark circuits with over ten thousands of gates. It takes only a minute to detect all testable faults and to identify all redundant faults of 20,000 gates circuit on a workstation.

We present algorithms for the optimization of sequential synchronous digital circuits using structural model, i.e. interconnections of combinational logic gates and synchronous registers. This approach contrasts traditional methods using state diagrams or transition tables and leveraging state minimization and encoding techniques. In particular, we model circuits by synchronous logic networks, that are weighted multigraphs representing interconnections of gates implementing scalar combinational functions. With this modeling style, area and path delays are explicit and their variation is easy to compute when circuit transformations are applied. Sequential logic optimization may target cycle-time or area minimization, possibly under area or cycle-time constraints. Optimization is performed by a sequence of transformations, directed to the desired goal. This paper describes the fundamental mechansms for transformations applicable to sequential circuits. We review first retiming and peripheral retiming techniques. The former method optimizes the position of the registers, while the latter repositions the registers to enlarge maximally the combinational region where combinational restructuring algorithms can be applied. We consider then synchronous algebraic and Boolean transformations, that blend combinational transformations with local retiming. Both classes of transformations require the representation of circuits by means of logic expressions with labeled variables, the labels representing discrete time-points. Algebraic transformations entail manipulation of time-labeled expressions with algebraic techniques. Boolean transformations exploit the properties of Boolean algebra and benefit from the knowledge of don't care conditions in the search for the best implementation of local functions. Expressing don't care conditions for sequential circuits is harder than for combinational circuits, because of the interaction of variables with different time labels. In addition, the feasibility of replacing a local function with another one may not always be verified by checking for the inclusion of the induced perturbation in local explicit don't care set. Indeed, the behavior of sequential circuits, that can be described appropriately by the relation between input and output traces, may require relational models to express don't care conditions. We describe a general formalism for sequential optimization by Boolean transformations, where the don't care conditions are expressed implicitly by synchronous recurrence equations. We present then an optimization method for this model, that can exploit degrees of freedom in optimization not possible for other methods, and hence providing solutions of possible superior quality. We conclude by summarizing the major features and limitations of optimization methods using structural models.

A new Viterbi algorithm with adaptive path reduction method is presented. The proposed system consists of the pre-decoder and reduced path Virerbi decoder. The predecoder separates the mixed channel noise from the received sequence. The number of errors in the pre-decoded error sequence is counted and the path reduction is implemented by the number of errors in pre-decoded error sequence. The path reduction is implemented as a function of channel condition because the errors in the pre-decoded error sequence can be considered as the channel error sequence. Due to the reduction of the path, the number of ACS (add compare select) operations can be reduced, which occupies the dominant part in Viterbi decoding. The ACS reduction ratio for the proposed system achieves up to 30% for the case of (2, 1, 2) Ungerboeck code without degradation of the error performance.

Bi2Sr2CuOx (Bi(2201)) thin films have been fabricated by atomic layer-by-layer deposition using ion beam sputtering (IBS) method. During the deposition, 14 wt%-ozone/oxygen mixture gas of typical pressure of 5.010-5 Torr is supplied with ultraviolet light irradiation for oxidation. XRD and RHEED investigations reveal that a buffer layer with compositions different from Bi(2201) is formed at the early deposition stage of less than 10 units cell and then Bi(2201) oriented along the c-axis is grown.

A sputtering system using dc hollow cathode discharge was developed for the propose of high Tc superconducting devices. Using this system, as-grown superconducting thin films of YBCO have been formed on MgO and SrTiO3 substrates. Influence of the sputtering conditions such as the substrate temperature and discharge gas pressure on the Tc and lattice parameter was investigated. It was found that superconducting films on MgO with Tczero higher than 87 K ere routinely obtained at the pressure of 820 mTorr (5%O2) and substrate temperature of 700 during deposition. The a/b-axis and c-axis oriented YBCO-PBCO hetero-structures were also successfully formed on MgO and SrTiO3 substrates.

We have calssified parenchymal echo patterns of cirrhotic liver into four types, according to the size of hypoechoic nodular lesions. Neural network technique has been applied to the characterization of hepatic parenchymal diseases in ultrasonic B-scan texture. We employed a multi-layer feedforward neural network utilizing the back-propagation algorithm. We carried out four kinds of pre-processings for liver parenchymal pattern in the images. We describe the examination of each performance by these pre-processing techniques. We show four results using (1) only magnitudes of FFT pre-processing, (2) both magnitudes and phase angles, (3) data normalized by the maximum value in the dataset, and (4) data normalized by variance of the dataset. Among the 4 pre-processing data treatments studied, the process combining FFT phase angles and magnitudes of FFT is found to be the most efficient.

In this paper we propose an architecture and an algorithm for the parallel execution of OPS5 production systems. It is known that current OPS5 production system interpreters spend almost 90% of their execution time in the match step. Thus, in this paper we focus on the speedup of the match step. The match algorithm used in OPS5 is called Rete and the algorithm uses a special kind of a date-flow network compiled from the left hand sides of rules. To achieve the maximum degree of parallelism of a given OPS5 program by as few processors as possible, the proposed parallel machine uses loosely coupled multiprocessors. Parallel machines designed for fine-grain parallelism, such as DADO, also use loosely coupled multiprocessors. However, the proposed machine differs from such machines at the following points: use of powerful processors which have large amounts of memories and small cycle times; use of a shared Rete network (parallel machines designed for fine-grain parallelism use an unshared Rete network); high hardware utilization. Basic ideas of the proposed parallel machine are as follows. (1) Use of a modified Rete network in which node sharing is used only for constant-test nodes and each memory node is lumped with the child two-input node. (2) Static allocation of the nodes of the modified Rete network onto processors. (3) Partition of the set of processors into three subsets: constant-test node processors, two-input node processors and conflict-set processors. (4) Use of a ring network for the interconnection network among two-input node processors. In addition to an architecture for parallel execution of OPS5 production systems, we propose a scheme for mapping the modified Rete network into the proposed architecture. The results of simulation experiments showed that the proposed architecture is promising for parallel execution of OPS5 production systems.

This paper describes a new automated approach to generating the patterns of CMOS leaf cells from transistor-level connectivity data. This method can generate CMOS leaf cells that are configurable to a macro cell satisfying user-specified constraints. The user-specified constraints include the aspect ratio and port positions of the macro cell. We propose a top-down method for converting the macro cell level constratints to leaf cell level ones. Using this method, a variety of customized macro cells can be designed in a short turn-around time. The method consists of four processes--diffusion sharing, initial placement, placement improvement and routing--which culminate in the automatic generation of symbolic representations. Using a compactor, those symbolic representations can be converted to physical patterns which are gathered into a macro cell by a macro generator. We define various objective functions to improve unit pair placement. We also introduce five ways to optimize leaf cell area: 1) multi-row division, 2) gate division 3) rotation, 4) power line and diffusion overlapping and 5) reconstruction of hierarchical structure. The proposed approach has been applied to various kinds of CMOS leaf cells. Experimental results show that the generated cells have almost the same areas as those generated by conventional bottom-up approaches in leaf and macro cell layouts. This approach offers a further advantage in that the various-sized macro cells required by layout disigners can also be generated.

A new circuit design of Josephson ternary δ-gate composed of Josephson junction devices is presented. Mathematical theory for synthesizing, analyzing, and realizing any given function in ternary system using Josephson ternary δ-gate is introduced. The Josephson ternary δ-gate is realized using SQUID technique. Circuit simulation results using J-SPICE demonstrated the feasibility and the reliability operations of Josephson ternary δ-gate with very high performances for both speed and power consumption (max. propagation delay time44 ps and max. power consumption2.6µW). The Josephson ternary δ-gate forms a complete set (completeness) with the ternary constants (1, 0, 1). The number of SQUIDs that are needed to perform the operation of δ-gate is 6. Different design with less than 6 SQUIDs is not possible because it can not perform the operation of δ-gate. The advantages of Josephson ternary δ-gate compared with different Josephson logic circuits are as follows: The δ-gate has the property that a simple realization to any given ternary logic function as the building blocks can be achieved. The δ-gate has simple construction with small number of SQUIDs. The δ-gate can realize a large number of ternary functions with small number of input/output pins. The performances of δ-gate is very high, very low power consumption and ultra high speed switching operation.

An algorithm interpolating parallel cross-sections between CT slices is described. Contours of equiscalar or constant-density surfaces on cross-sections are directly obtained as non-intersecting loops from grayscale slice images. This algorithm is based on a general algorithm that the authors have proposed earlier, constructing triangulated orientable closed surfaces from grayscale volumes and is particularly suited for a new technique, called laser stereolithography, which creates real 3D plastic objects using UV laser to scan and harden liquid polymer. The process of laser stereolithography is executed slice by slice, and this technique really requires some interpolation of intermediate cross-sections between slices. For visualizing, surfaces are only expected to be shaded almost continuously. The local defects are invisible and not cared about if the picture resolution is rather poor. On the contrary, topological faults are fatal to construct solid models by laser stereolithography, i.e., every contour line on cross-sections must be closed with no intersection. Not a single break of a contour line is tolerated. We already have many algorithms available for equiscalar surface construction, and it seems that if we cut the surfaces, then contour lines could be obtained. However, few of them are directly applicable to solid modeling. Marching cubes algorithm, for example, does not ensure the consistency of surface topology. Our algorithm guarantee an adequate topology of contour lines.

A hardware algorithm for modular inversion is proposed. It is based on the extended Euclidean algorithm. All intermediate results are represented in a redundant binary representation with a digit set {0, 1,1}. All addition/subtractions are performed without carry propagation. A modular inversion is carried out in O (n) clock cycles where n is the word length of the modulus. The length of each clock cycle is constant independent of n. A modular inverter based on the algorithm has a regular cellular array structure with a bit slice feature and is very suitable for VLSI implementation. Its amount of hardware is proportional to n.

In this paper, we define an attributed random graph, which can be considered as a generalization of conventional ones, to include multiple attributes as well as numeric attribute instead of a single nominal attribute in random vertices and edges. Then we derive the probability equations for an attributed graph to be an outcome graph of the attributed random graph, and the equations for the entropy calculation of the attributed random graph. Finally, we propose the application areas to computer vision and machine learning using these concepts.

A network-topology-independent static task allocation strategy has been designed and implemented for massively parallel computers. For mapping a task graph to a processor graph, this strategy evaluates several functions that represent some intuitively feasible properties or the graphs. They include the connectivity with the allocated nodes, distance from the median of a graph, connectivity with candidate nodes, and the number of candidate nodes within a distance. Several greedy strategies are defined to guide the mapping process, utilizing the indicated function values. An allocation system has been designed and implemented based on the allocation strategy. In experiments we have defined about 1000 nodes in task graphs with regular and irregular topologies, and the same order of processors with mesh, tree, and hypercube topologies. The results are summarized as follows. 1) The system can yield 4.0 times better total communication costs than an arbitrary allocation. 2) It is difficult to select a single strategy capable of providing the best solutions for a wide range of task-processor combinations. 3) Comparison with hypercube-topology-dependent research indicates that our topology-independent allocator produces better results than the dependent ones. 4) The order of computaion time of the allocator is experimentally proved to be O (n2) where n represents the number of tasks.

The barrier-layer was successfully fabricated for a preparation of tunneling junction using high Tc oxidesuperconductor such as Bi-Sr-Ca-Cu-O system. Bi2Sr2Ca2Cu3Ox films were used for both superconducting electrodes and the barrier was mainly Bi2Sr2CaCu2O and the rest that was formed by effects of de-calcium from the first sputtered (2223) film. The reaction of de-calcium occurred immersing it in carbonated water. The change of (2223) phase of BSCCO was confirmed with a comparison of the intensity of X-ray diffraction. The superconductive transition temperature of the junction is different from that of the single film (2223) which had no treatment with carbonated water. Zero-bias-currents through fabricated barrier are observed and the critical currents depend on temperature so far as measured temperature region of 79 K-72 K.

We developed programmable high-performance and high-speed neurocomputer for a large neural network using ASIC neurocomputing chips made by CMOS VLSI technology. The neurocomputer consists of one master node and multiple slave nodes which are connected by two data paths, a broadcast bus and a ring bus. The nodes are made by ASIC chips and each chip has plural nodes in it. The node has four types of computation hardware that can be cascaded in series forming a pipeline. Processing speed is proportional to the number of nodes. The neurocomputer is built on one printed circuit board having 65 VLSI chips that offers 1.5 billion connections/sec. The neurocomputer uses SIMD for easy programming and simple hardware. It can execute complicated computations, memory access and memory address control, and data paths control in a single instruction and in a single time step using the pipeline. The neurocomputer processes forward and backward calculations of multilayer perceptron type neural networks, LVQ, feedback type neural networks such as Hopfield model, and any other types by programming. To compute neural computation effectively and simply in a SIMD type neurocomputer, new processing methods are proposed for parallel computation such as delayed instruction execution, and reconfiguration.

The recent non von Neumann chip architectures are mainly classified into the AI architecture and the neural architecture. We focus on these two categories, and introduce the representatives each with a brief history. The AI chip architecture is difficult to escape essentially from the von Neumann architecture as far as it is language-oriented. The neural architecture, however, may yield an essentially new computer architecture, when the new device technologies will support it. In particular, the optoelectronics and the quantum electronics will provide a lot of powerful technologies.

The authors examined the effect of feedbacking information on learners of their test results obtained through computerized tests. The learner's acceptability of computerized tests was revealed to be improved by distribution and explanation of newly devised feedback charts including data on one's response history and response latency during computerized testing that was carried out in formative evaluation. The feedback chart composed of graphic representation of relationship between degree of difficulty of each question and its response latency got a particularly high evaluation among learners. It was revealed that types of feedback chart that stood highest in learner's estimate varied with the learner traits. This observation will serve to develop educational systems that incorporate computerized tests into school lessons.

Three dimensional (3-D) optics offers potential advantages to the massively-parallel systems over electronics from the view point of information transfer. The purpose of this paper is to survey some aspects of the 3-D optical interconnection technology for the future massively-parallel computing systems. At first, the state-of-art of the current optoelectronic array devices to build the interconnection networks are described, with emphasis on those based on the semiconductor technology. Next, the principles, basic architectures, several examples of the 3-D optical interconnection systems in neural networks and multiprocessor systems are described. Finally, the issues that are needed to be solved for putting such technology into practical use are summarized.

In this letter, we study on the sensitivity to the electrical stimulus pulse for biomedical electronics for the purpose to make a tactile vision substitution system for binds. We derive the equivalent circuit of finger by measuring sensitive voltages with various touch condition and various DC voltage. And we consider to the sensitivity of finger against electrical stimulus pulse. In order to convert the sense of sight to tactile sense, we consider four types of touch condition and various types of pulse. It is shown that the sensitivity of finger to electrical stimulus pulse is determined by duty-ratio, frequency, hight of pulse and the type of touch condition. In the case that duty-ratio is about 20%, frequency is within about 60-300Hz and touch condition is A-4 type, the sensitive voltage becomes the lowest. With this result, a tactile vision substitution system can be developed and the system will be used to transfer various infomations to blinds without paper.

Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper proposes a new multiple-valued code assignment algorithm to implement locally computable combinational circuits for k-ary operations. By the decomposition of a given k-ary operation into unary operations, a code assignment algorithm for k-ary operations is developed. Partition theory usually used in the design of sequential circuits is effectively employed for optimal code assignment. Some examples are shown to demonstrate the usefulness of the proposed algorithm.