An all CMOS variable gain amplifier (VGA) which features wide dB-linear gain range per stage (45 dB), low power consumption (1.32 mW), small chip size (0.13 mm2), and low supply voltage (1.2 V) is described. The dB-linear range is extended by reducing the supply voltage of the conventional V-to-I converter. The two-stage VGA implemented in 0.18 µm CMOS offers 90 dB of gain variation, 3 dB bandwidth of greater than 21 MHz, and max/min input IP3 and P1 dB, respectively, of -5/-42 and -12/-50 dBm.

In [13], we proposed new decision problems related to lattices, and proved their NP-completeness. In this paper, we present a new public-key identification scheme and a digital signature scheme based on one of the problems in [13]. We also prove the security of our schemes under certain assumptions, and analyze the efficiency of ours.

In this paper, characteristics of the 2-bit recessed channel memory with lifted-charge trapping nodes are investigated. The length between the charge trapping nodes through channel, which is defined as the effective memory node length (Meff), is extended by lifting up them. The dependence of VTH window and short channel effect (SCE) on the recessed depth is analyzed. Improvement of short channel effect is achieved because the recessed channel structure increases the effective channel length (Leff). Moreover, this device shows highly scalable memory characteristics without suffering from the bottom-side effect (BSE).

The management of subscriptions and events is an important task in the content-based publish/subscribe system. A good management mechanism can not only produce lower matching costs to speed up the delivery of matched events to the interested subscribers but can also induce good load balancing for subscription storage. In this paper, we consider the construction of this kind of system over a peer-to-peer overlay network and propose two message-to-node mapping schemes for system management. We both analyze and simulate the performance of the proposed schemes. The simulation results show the superiority of our schemes over existing ones.

In heterogeneous network environments, it is mandatory to measure the grade of the video quality in order to guarantee the optimal quality of the video streaming service. Quality of Service (QoS) has become a key issue for service acceptability and user satisfaction. Although there have been many recent works regarding video quality, most of them have been limited to measuring quality within temporal and Signal-to-Noise Ratio (SNR) scalability. H.264/AVC Scalable Video Coding (SVC) has emerged and has been developed to support full scalability. This includes spatial, temporal, and SNR scalability, each of which shows different visual effects. The aim of this paper is to define and develop a novel video quality metric allowing full scalability. It focuses on the effect of frame rate, SNR, the change of spatial resolution, and motion characteristics using subjective quality assessment. Experimental results show the proposed quality metric has a high correlation to subjective quality and that it is useful in determining the video quality of SVC.

This paper presents discussion about channel fluctuation on channel estimation in digital terrestrial television broadcasting. This channel estimation uses a two-dimensional (2D) filter. In our previous work, only a structure of a lattice is considered for generation of nonrectangular 2D filter. We investigate generation of nonrectangular 2D filter with adaptive method, because we should refer to not only a lattice but also channel conditions. From the computer simulations, we show that bit error rate of the proposed filter is improved compared to that of the filter depending on only lattices.

Instruction issue queue is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction queue size should be increased. However, it is difficult to increase the size, since instruction queue is implemented by a content addressable memory (CAM) whose power and delay are much large. This paper introduces a low power and scalable instruction queue that replaces the CAM with a RAM. In this queue, instructions are explicitly woken up. Evaluation results show that the proposed instruction queue decreases processor performance by only 1.9% on average. Furthermore, the total energy consumption is reduced by 54% on average.

This paper proposes the minimum transition random X-filling (MTR-fill) technique, which is a new X-filling method, to reduce the amount of power dissipation during scan-based testing. In order to model the amount of power dissipated during scan load/unload cycles, the total weighted transition metric (TWTM) is introduced, which is calculated by the sum of the weighted transitions in a scan-load of a test pattern and a scan-unload of a test response. The proposed MTR-fill is implemented by simulated annealing method. During the annealing process, the TWTM of a pair of test patterns and test responses are minimized. Simultaneously, the MTR-fill attempts to increase the randomness of test patterns in order to reduce the number of test patterns needed to achieve adequate fault coverage. The effectiveness of the proposed technique is shown through experiments for ISCAS'89 benchmark circuits.

The single-hidden-layer feedforward neural networks (SLFNs) are frequently used in machine learning due to their ability which can form boundaries with arbitrary shapes if the activation function of hidden units is chosen properly. Most learning algorithms for the neural networks based on gradient descent are still slow because of the many learning steps. Recently, a learning algorithm called extreme learning machine (ELM) has been proposed for training SLFNs to overcome this problem. It randomly chooses the input weights and hidden-layer biases, and analytically determines the output weights by the matrix inverse operation. This algorithm can achieve good generalization performance with high learning speed in many applications. However, this algorithm often requires a large number of hidden units and takes long time for classification of new observations. In this paper, a new approach for training SLFNs called least-squares extreme learning machine (LS-ELM) is proposed. Unlike the gradient descent-based algorithms and the ELM, our approach analytically determines the input weights, hidden-layer biases and output weights based on linear models. For training with a large number of input patterns, an online training scheme with sub-blocks of the training set is also introduced. Experimental results for real applications show that our proposed algorithm offers high classification accuracy with a smaller number of hidden units and extremely high speed in both learning and testing.

Feature transformation in automatic text classification (ATC) can lead to better classification performance. Furthermore dimensionality reduction is important in ATC. Hence, feature transformation and dimensionality reduction are performed to obtain lower computational costs with improved classification performance. However, feature transformation and dimension reduction techniques have been conventionally considered in isolation. In such cases classification performance can be lower than when integrated. Therefore, we propose an integrated feature analysis approach which improves the classification performance at lower dimensionality. Moreover, we propose a multiple feature integration technique which also improves classification effectiveness.

This paper proposes a task scheduling approach for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable SRAMs under real-time constraints. A mixed integer programming model has been built for minimizing vulnerability under real-time constraints. Experimental results have shown that our task scheduling approach achieved 47.7-99.9% less vulnerability than a conventional one.

Fair queueing is a service scheduling discipline to pursue the fairness among users in packet communication networks. Many fair queueing algorithms, however, have problems of computational overhead since the central scheduler has to maintain a certain performance counter for each flow of user packets based on the global virtual time. Moreover, they are not suitable for wireless networks with high probability of input channel errors due to the lack or complexity in the compensation mechanism for the recovery from the error state. In this paper, we propose a new, computationally efficient, distributed fair queueing scheme, which we call Channel-Aware Throughput Fair Queueing (CATFQ), that is applicable to both wired and wireless packet networks. In our CATFQ scheme, each flow is equipped with a counter that measures the weighted throughput achievement while it has a backlog of packets. At the end of every service to a packet, the scheduler simply selects a flow with the minimum counter value as the one from which a packet is served next. We show that the difference between any two throughput counters is bounded. Our scheme significantly reduces the scheduler's computational overhead and guarantees fair throughput for all flows. For wireless networks with error-prone channels, the service chance lost in bad channel condition is compensated quickly as the channel recovers. Our scheme suppresses the service for leading flows, brings short-term fairness for flows without channel errors, and achieves long-term fairness for all flows. These merits are verified by simulation.

The problem of joint orthogonal precoding and user scheduling in a multi-user multi-input multi-output (MU-MIMO) downlink system is considered. Based on the theoretics of subspace and vector projection, a novel orthogonal precoding matrix is designed to achieve high sum-rate capacity with low to moderate number of active users and in low SNR regions. With respect to sum-rate capacity, numerical simulations show that the proposed algorithm outperforms the zero-forcing beam-forming (ZFBF) and linear orthogonal beam-forming (OLBF).

This paper proposes a novel Behavioral Synthesis method that tries to reduce the number of clock cycles under clock cycle time and total functional unit area constraints using special functional units efficiently. Special functional units are designed to have shorter delay and/or smaller area than the cascaded basic functional units for specific operation patterns. For example, a Multiply-Accumulator is one of them. However, special functional units may have less flexibility for resource sharing because intermediate operation results may not be able to be obtained. Hence, almost all conventional methods can not handle special functional units efficiently for the reduction of clock cycles in practical time, especially under a tight area constraint. The proposed method makes it possible to solve module selection, scheduling, and functional unit allocation problems using special functional units in practical time with some heuristics. Experimental results show that the proposed method has achieved maximally 33% reduction of the cycles for a small application and 14% reduction for a realistic application in practical time.

In this letter, we propose new modifications of current routing protocol to fully utilize the multihoming functionality of SCTP over MANET. To achieve this, multiple address allocation and disjoint path setup schemes in a reactive routing protocol are developed under a cross-layer concept. We demonstrate that two newly added features contribute to higher SCTP throughput than original one.

This paper proposes a method to generate exceptional scenarios from a normal scenario written with a scenario language. This method includes (1) generation of exceptional plans and (2) generation of exceptional scenario by a user's selection of these plans. The proposed method enables users to decrease the omission of the possible exceptional scenarios in the early stages of development. The method will be illustrated with some examples.

This paper proposes a new type of layered video coding especially for the use of monitoring water level of a river. A sensor node of the system decomposes an input video signal into some kinds of component signals and produces a bit stream functionally separated into three layers. The first layer contains the minimum components effective for detecting the water level. It is transmitted at very low bit rate for regular monitoring. The second layer contains signals for thumb-nail video browsing. The third layer contains additional data for decoding the original video signal. These are transmitted in case of necessity. A video signal is decomposed into several bands with the three dimensional Haar transform. In this paper, optimum bands to be contained into the 1st layer are experimentally investigated considering both of water level detection and data size to be transmitted. As a result, bit rate for transmitting the first layer is reduced by 32.5% at the cost of negligible 3.7% decrease of recognition performance for one of video examples.

This letter presents the first experimental results that confirm the restorability of Rayleigh backscatter traces from a single-mode fiber measured by using a coherent optical time domain reflectometer (OTDR) with a precisely frequency-controlled light source. Based on this restorability, we can measure the distributed strain and temperature along the fiber with a very high measurand resolution that is one to two orders of magnitude better than that provided by Brillouin-based techniques for a long length of fiber.

Developing LSIs with EMI suppression, particularly for use in automobiles, is important for improving warranties and customer acquisition. First, we describe that the measures against EMI noise caused by a X'tal oscillator are important. Next, we present a practical method for analyzing the noise with models of the inside and outside of a chip. In addition, we propose a within-chip measure against EMI noise that takes chip cost into account. The noise is suppressed by using an appropriate resistance and capacitance on the power line. Simulation results demonstrated the method's effectiveness in suppressing noise.

This paper presents a processor architecture for high-speed and reliable trinocular stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on regularity of reference pixels. The stereo matching processor is designed in a 0.18 µm CMOS technology. The processing time is 83.2 µs@100 MHz. By using optimal scheduling, the increases in area and processing time is only 5% and 3% respectively compared to binocular stereo vision although the computational amount is double.