Per-Virtual Connection (VC) queueing allows an ATM switch to schedule cells to be transmitted on a link based on their VC. This alternative to the traditional First-In-First-Out(FIFO)queueing, in which cells from different VCs of the same priority are stored in a common queue, is implemented by some switch manufacturers. This paper assesses the merits of per-VC scheduling in regards to capacity, traffic shaping, and interworking with traffic management mechanisms such as connection admission control (CAC) and use of queue thresholds. The paper also discusses the conditions which favor the use of per-VC scheduling.

An oversampling theorem for regular sampling in wavelet subspaces is established. The sufficient-necessary condition for which it holds is found. Meanwhile the truncation error and aliasing error are estimated respectively when the theorem is applied to reconstruct discretely sampled signals. Finally an algorithm is formulated and an example is calculated to show the algorithm.

An MMIC variable-gain amplifier, which improves the transmission phase deviation caused by gain control, is presented. At first, it is shown that by controlling both the common-gate FET's gate bias voltage and the common-source FET's gate bias voltage, the transmission phase deviation caused by gain control of the variable-gain amplifier using a cascode-connected FET is greatly improved. In this case it is not desirable to control both of the gate bias voltages independently, because of the complexity. Thus we propose two simple gate bias voltage control circuits controlling both of the gate bias voltages, in which only one of the two gate bias voltages is controlled independently and the other is controlled dependently. Then we apply these circuits to the 1. 9-GHz-band variable-gain amplifier using the cascode-connected FET. One of the control circuits is the gate bias voltage control circuit using two resistors. It is confirmed that, by applying the newly proposed circuit, phase deviation is suppressed, from between 0and 30to between 3and 5, with 25-dB gain control. The other circuit is the gate bias voltage control circuit using the FET's nonlinear characteristics. It is confirmed that, by applying the newly proposed circuit, phase deviation is suppressed, from between 0and 44to between 6and 3 with 30-dB gain control. This is a promising technique for reducing the transmission phase deviation caused by gain control of the amplifiers used in active phased array antennas.

We present a new scheduling policy named Value-based Processor Allocation (VPA-k) for scheduling value-based transactions in a multiprocessor real-time database system. The value of a transaction represents the profit the transaction contributes to the system if it is completed before its deadline. Using VPA-k policy, the transactions with higher values are given higher priorities to execute first, while at most k percentage of the total processors are allocated to the urgent transactions dynamically. Through simulation experiments, VPA-k policy is shown to outperform other scheduling policies substantially in both maximizing the totally obtained values and minimizing the number of missed transactions.

Parallelism on heterogeneous machines brings cost effectiveness, but also raises a new set of complex and challenging problems. This paper addresses the problem of estimating the minimum time taken to execute a program on a fine-grained parallel machine composed of different types of processors. In an earlier publication, we took the first step in this direction by presenting a graph-construction method which partitions a given program into several homogeneous parts and incorporates timing constraints due to heterogeneous parallelism into each part. In this paper, to make the method easier to be applied in a scheduling framework and to demonstrate its practical utility, we present an efficient implementation method and compare the results of its use to the optimal schedule lengths obtained by enumerating all possible solutions. Experimental results for several different machine models indicate that this method can be effectively used to estimate a program's minimum execution time.

This paper proposes practical escrow cash schemes with particular emphasis on countermeasures against social crimes such as money laundering and extortion. The proposed cash schemes restrict "unconditional" privacy in order to prevent these social crimes while preserving off-line-ness, divisibility and transferability, properties listed in [25] as criteria for ideal cash schemes.

Gate performance for observing Coulomb oscillations and Coulomb diamonds are compared for two types of gated sub-µm double-barrier heterostructures. The first type of device contains modulation-doped barriers, whereas the second type of device contains a narrower band gap material for the well and no barriers with doped impurities. Both the Coulomb oscillations and Coulomb diamonds are modified irregularly as a function of gate voltage in the first type of device, while in the second type of device they are only systematically modified, reflecting atom-like properties of a quantum dot. This difference is explained in terms of the existence of impurities in the first type of device, which inhomogeneously deform the rotational symmetry of the lateral confining potential as the gate voltage is varied. The absence of impurities is the reason why we observe the atom-like properties only in the second type of device.

An econominal implementation of a chaos circuit onto the hardware is an important subject. In this letter, a two-dimensional digital chaos circuit realizing a Henon map is designed. Concerning the attractor and the bifurcation diagram of the proposed circuit, numerical simulations are performed to confirm the validity of the circuit algorithm. Furthermore, the proposed digital chaos circuit is designed by Verilog-HDL (Hardware Description Language). The proposed digital chaos circuit can be implemented into the form of the FPGA (Field Programmable Gate Array).

Fiat-Shamir's identification and signature scheme is efficient as well as provably secure, but it has a problem in that the transmitted information size and memory size cannot simultaneously be small. This paper proposes an identification and signature scheme which overcomes this problem. Our scheme is based on the difficulty of extracting theL-th roots modn (e. g.L=2 1020) when the factors ofnare unknown. We prove that the sequential version of our scheme is a zero knowledge interactive proof system and our parallel version reveals no transferable information if the factoring is difficult. The speed of our scheme's typical implementation is at least one order of magnitude faster than that of the RSA scheme and is relatively slow in comparison with that of the Fiat-Shamir scheme.

We propose a new method for verifying synchronous circuits using the Boyer-Moore Theorem Prover (BMTP) based on an efficient use of induction. The method contains two techniques. The one is the representation method of signals. Each signal is represented not as a waveform, but as a time parameterized function. The other is the mechanical transformation of the circuit description. A simple description of the logical connection of the components of a circuit is transformed into such a form that is not only acceptable as a definition of BMTP but also adequate for applying induction. We formalize the method and show that it realizes an efficient proof.

We analyze M,MMPP/G/1 finite queues with queue-length-threshold (QLT) scheduling policy and Bernoulli schedule where the arrival of type-1 customers (nonreal-time traffic) is Poisson and the arrival of type-2 customers (real-time traffic) is a Markov-modulated Poisson process (MMPP). The next customer to be served is determined by the queue length in the buffer of type-1 customers. We obtain the joint queue length distribution for customers of both types at departure epochs by using the embedded Markov chain method, and then obtain the queue length distribution at an arbitrary time by using the supplementary variable method. From these results, we obtain the loss probabilities and the mean waiting times for customers of each type. The numerical examples show the effects of the QLT scheduling policy on performance measures of the nonreal-time traffic and the bursty real-time traffic in ATM networks.

This letter proposes a Perfect-Reconstruction (PR) encryption scheme based on a PR QMF bank. Using the proposed scheme, signals can be encrypted and reconstructed perfectly by using two Periodically Time-Varying (PTV) digital filters respectively. Also we find that the proposed scheme has a "good" encryption effect and compares favorably with frequency scramble in the aspects of computation complexity, PR property, and degree of security.

This paper proposes high-speed similitude retrieval schemes for a viewpoint-based similarity discrimination system (VB-SDS) and presents analytical and experimental performance evaluations. The VB-SDS, which contains a huge set of semantic definitions of commonly used words and computes semantic similarity between any two words under a certain viewpoint, promises to be a very important module in analogical and case-based reasoning systems that provide solutions under uncertainty. By computing and comparing similarities for all words contained in the system, the most similar word for a given word can be retrieved under a given viewpoint. However, the time this consumes makes the VB-SDS unsuitable for inference systems. The proposed schemes reduce search space based on the upper bound of a similarity calculation function to increase retrieval speed. An analytical evaluation shows the schemes can achieve a thousand-fold speedup and confirmed through experimental results for a VB-SDS containing about 40,000 words.

This paper proposes an analysis method of scaling-factor-quantization error in fractal image coding using a state-space approach with the statistical analysis method. It is shown that the statistical analysis method is appropriate and leads to a simple result, whereas the deterministic analysis method is not appropriate and leads to a complex result for the analysis of fractal image coding. We derive the output error variance matrix for the measure of error and define the output error variance by scalar quantity as the mean of diagonal elements of the output error variance matrix. Examples are given to show that the scaling-factor-quantization error due to iterative computation with finite-wordlength scaling factors degrades the quality of decoded images. A quantitative comparison of experimental scaling-factor-quantization error with analytical result is made for the output error variance. The result shows that our analysis method is valid for the fractal image coding.

This paper describes the design and architecture for a newly developed microprocessor suitable for consumer applications, which we call SuperH. To achieve both low-power and high-speed, the SuperH architecture includes 16-bit fixed length instruction code and several power saving features. The 16-bit fixed length instruction code makes the SuperH possible to achieve excellent code efficiency for the SPECint benchmarks when compared with conventional microcontrollers and RISC's for workstations and PC's. As a result, the SuperH provides almost the same code efficiency as that of 8-bit microcontrollers, and also achieves similar performance as that of RISC's with 32-bit fixed length instruction code. The SuperH also incorporates several power reduction techniques through the control of clock frequency and clock distribution. Thus, the 16-bit code format, power saving features, and other architectural innovations make the SuperH particularly proficient for portable multi-media applications.

The proposed high-power-factor converter is constructed with a flyback converter, and locates the energy-storage capacitor on the secondary side of the transformer. A high power-factor can be obtained without needing to detect any current, and the ZVS operation can be achieved without auxiliary switches. To make the best use of these advantages in the converter, ZVS operations and power-factor characteristics in the converter were analyzed. From the analytical results, the effective control method for achieving ZVS was examined. Using a bread-board circuit controlled by this method, a power-factor of 0.99 and a conversion efficiency of 88% were measured.

In supervisory control, discrete event dynamic systems (DEDSs) are modeled by finite-state automata, and their behaviors described by the associated formal languages; control is exercised by a supervisor, whose control action is to enable or disable the controllable events. In this paper we present a general stability concept for DEDSs, stability in the sense of Lyapunov with resiliency, by incorporating Lyapunov stability concepts with the concept of stability in the sense of error recovery. We also provide algorithms for verifying stability and obtaining a domain of attraction. Relations between the notion of stability and the notion of fault-tolerance are addressed.

A switched-capacitor Wien bridge oscillator and its automatic gain controller are discussed for low-frequency generation. The dc voltage Vs related to the amplitude of oscillation is obtained from the voltage differences in the frequency-determining arm. Theoretical analysis of the ripples in Vs is reported.

In general cases of pattern recognition, a pattern to be recognized is first represented by a set of features and the measured values of the features are then classified. Finding features relevant to recognition is thus an important issue in recognizer design. As a fundamental design framework taht systematically enables one to realize such useful features, the Subspace Method (SM) has been extensively used in various recognition tasks. However, this promising methodological framework is still inadequate. The discriminative power of early versions was not very high. The training behavior of a recent discriminative version called the Learning Subspace Method has not been fully clarified due to its empirical definition, though its discriminative power has been improved. To alleviate this insufficiency, we propose in this paper a new discriminative SM algorithm based on the Minimum Classification Error/Generalized Probabilistic Descent method and show that the proposed algorithm achieves an optimal accurate recognition result, i.e., the (at least locally) minimum recognition error situation, in the probabilistic descent sense.

This paper presents a proportional-share CPU scheduler which can support multimedia applications in a general-purpose workstation environment. For this purpose, we have extended the stride scheduler which is designed originally for conventional tasks. New scheduling parameters are introduced to specify timing requirements of multimedia applications. Through the use of the rate regulator, the accuracy error of the scheduling is reduced to 0 (1). Separate task groups are proposed to represent both relative shares and absolute shares. The proposed scheduler is evaluated using a simulation study. The results show that the proposed scheduler achieves improved accuracy and adaptability as well as flexibility.