One of the polarimetric radar applications is classification or identification of targets making use of the scattering matrix. This paper presents a decomposition scheme of a scattering matrix into three elementary scattering matrices in the circular polarization basis. The elementary components are a sphere, a diplane (dihedral corner reflector), and a helix. Since a synthetic aperture FM-CW radar provides scattering matrix through a polarimetric measurement, this decomposition scheme was applied to the actual raw data, although the matrix is resulted from a swept frequency measurement. Radar imaging experiments at the Ku band (14.5-15.5GHz) were carried out to obtain a total of 6464 scattering matrices in an imaging plane, using flat plates, corner reflectors and wires as elementary radar targets for classification. It is shown that the decomposition scheme has been successfully carried out to distinguish these targets and that the determination of rotation angle of line target is possible if the scattering matrix is classified as a wire.

Most of current real time video retrieval systems use video transfer protocols such that servers simply transmit video packets in the same rate as clients play them. If any packets are corrupted during transmission, they will be lost and cannot be recovered by retransmission. In video retrieval systems, however, teh video data are stored in servers and clients can prefetch them prior to playing. So, it might be possible for the video retrieval systems to make corrupted video packets retransmitted before the play-out dead line. But the application of existing reliable protocols causes problems such that, if a packet does not arrive before the dead line due to retransmission, the packets following it will not be delivered to the upper layer even if they have already arrived. In this paper, we discuss how to apply reliable protocols to real time video retrieval systems and propose an new real time video transfer protocol over ATM network, which provides the video data prefetch, the flow control for video buffer, the selective retransmission with skipping function for video packets late for the play-out dead line, and the resynchronization function for video buffer. We have implemented an experimental system using our protocol and evaluated the performance. The results of performance evaluation shows that the proposed protocol decreases the number of unplayed video data largely when transmission errors are inserted in an ATM network.

A novel CMOS half-wave rectifying transconductor is presented. The proposed circuit utilizes a simple new cascode current subtracter which is obtained from conventional cascode current mirror by a judicious reconfiguration to yield additional subtrahend signal path. The simulated DC transfer characteristics is highly linear with 1.1% linearity error up to 1.5V differential input voltage and the blunt corner at zero-crossing is 20mV. The output resistance is greater than 23MΩ and the total harmonic distortions at 100kHz with 1.5Vp-p in the positive half cycle are better than -46.5dB. The usable operating frequencies are up to 10MHz with maximum peak-to-peak input voltage and 75µW power consumption.

Recently, two new efficient server-aided RSA secret computation protocols were proposed. They are efficient and can guard against some active attacks. In this letter, we propose two multi-round active attacks which can effectively reduce their security level even break them.

For the completely polarized wave case, this paper presents the explicit formulae of the characteristic polarization states in the co-polarized radar channel, from which one can obtain the CO-POL Max, the CO-POL Saddle and the CO-POL Nulls in the Stokes vector form. Then the problem on the polarimetric contrast optimization is discussed, and the explicit formula of the optimal polarization state for contrast enhancement is presented in the Stokes vector form for the first time. To verify these formulae, we give some numerical examples. The results are completely identical with other authors', which shows the validity of the presented method.

Satellite beam-switching problems are studied where there are m up-link beams, n down-link beams and multiple carriers per beam. By augmenting a traffic matrix with an extra row and column, it is possible to find a sequence of switching modes ((0,1)-matrices with genrally multiple unit entries in each row and column) that realize optimal transmission time. Switching modes generated are shown to be linearly independent. The number of switching modes required for an mn matrix is bounded by (m1)(n1)1. For an augmented (m1)(n1) matrix, the bound is then mn1. The bounds on the number of switching modes and the computational complexity for a number of related satellite transmission scheduling problems are lowered. In simplified form, the results (particularly the linear independence of permutation matrices generated) apply to algorithmic decomposition of doubly stochastic matrices into convex combinations of permutation matrices.

To implement the PGPS packet scheduling algorithm in high speed networks is more difficult since it is based on real time simulation of an equivalent fluid-model system leading to a higher implementation time complexity. A modified approach to PGPS is the SCFQ scheme. This scheme is easy to implement, but has an increasing end-to-end delay bound. The VC packet scheduling algorithm provides the same end-to-end delay bound as PGPS does, but has the disadvantage of unfairness. As SCFQ, SFQ is much easier to implement than PGPS and achieves the same fairness, but has a higher end-to-end delay bound than PGPS. We propose a new packet scheduling algorithm, called Minimum Starting-tag Fair Queueing (MSFQ), which assigns the virtual time to be the minimum starting tag over all backlogged connections. MSFQ is much easier to implement than PGPS and provides the same end-to-end delay bound for each connection and fairness as PGPS. In this paper, we will show the end-to-end delay bound and fairness of MSFQ and compare 5 rate-based packet scheduling algorithms including PGPS, VC, SCFQ, SFQ, and MSFQ focusing on end-to-end delay bound, fairness, and implementation time complexity.

A new current-mode sampled-data chaos circuit is proposed. The proposed circuit is composed of an operation block, a parameter block, and a delay block. The nonlinear mapping functions of this circuit are generated in the neuro-fuzzy based operation block. And these functions are determined by supervised learning. For the proposed circut, the dynamics of the learning and the state of the chaos are analyzed by computer simulations. The design conditions concerning the bifurcation diagram and the nonlinear mapping function are presented to clarify the chaos generating conditions and the effect of nonidealities of the proposed circuit. The simulation results showed that the nonlinear mapping functions can be realized with the precision of the order of several percent and that different kinds of bifurcation modes can be generated easily.

Advanced scientific and engineering problems require massively parallel computing. Critical to the designand ultimately the performanceof such computing systems is the interconnection network binding the computing elements, just as is the cardiovascular network to the human body. This paper develops a new interconnection network, "Tori connected mESHes (TESH)," consisting of k-ary n-cube connection of supernodes that comprise meshes of lower level nodes. Its key features are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion (up to a million processors), and it appears to be well suited for 3-D VLSI implementation, for it requires far fewer number of vertical wires than almost all known multi-computer networks. Presented in the paper are the architecture of the new network, node addressing and message routing, 3-D VLSI/ULSI considerations, and application of the network to massively parallel computing. Specifically, we discuss the mapping on to the network of stack filtering, a hardware oriented technique for order statistic image filtering.

It is well known that offset errors in the multipliers of neural LSIs can have fatal effects on performance. The aim of this study is to understand theoretically how offset errors affect performance of neural LSIs. We have used a single-layer perceptron as an example, and compare our theoretically derived results with computer simulations. We have found that offset errors in the multipliers for the forward process can be canceled out through learning, but those for the updating process cannot be. We have examined the asymptotic behavior of learning for the updating process and derived a mathematical expression for dL, the excess of the averaged loss function L. The derived expression gives us a basis for estimating robustness with respect to the offset errors. Our analysis indicates that dL can be expressed in the form of a quadratic form of offset errors and the inverse of the Hessian matrix of L. We have found that increasing the number of synapses degrades the performacne. We have also learned that enlarging the input signal level and reducing the signal level of the desired response can be effective techniques for reducing the effects of offset errors of the updating process.

This paper proposes a high-speed crosspoint-buffer-type ATM switch, named Scalable-Distributed -Arbitration (SDA) switch. The SDA switch employs a new arbitration scheme that allows the switch to be scalable. The SDA switch has a crosspoint buffer and a transit buffer at every crosspoint. Arbitration is executed between the crosspoint buffer and the transit buffer. The arbitration selects a cell based on delay time using a synchronous counter. The selected cell is transferred from a crosspoint buffer to the output port by way of several transit buffers. Since arbitration is executed in a distributed manner at each crosspoint and the arbitration time does not depend on the switch size, the SDA switch can be expanded to realize large throughput. Numerical results show that the SDA switch ensures fairness in terms of delay time. In addition, the maximum delay time and the required crosspoint buffer size of the SDA switch are reduced, compared with those in the conventional switch based on ring arbitration. Thus, the proposed SDA switch based on the new arbitration scheme has a simple and expandable architecture,and will be suitable for future high-speed multimedia ATM networks.

This peper proposes a simplified model of the well-known two-neuron neural oscillator. By eliminating one of the two positive feedback synapses in the neural oscillator, learning for the in-phase control of the oscillator is shown to be achievable via a very simple learning rule. The learning rule is devised in such a way that only the plasticity of two synaptic weights are required. We demonstrate some examples of the synchronization learning to validate the efficiency of the learning rule, and finally by illustrating the dynamics of the synchronization learning and by using computer simulation, we show the convergence behavior and the stability of the learning rule for the two-neuron simple neural oscillator.

In order to construct fuzzy systems automatically, there are many studies on combining fuzzy inference with neural networks. In these studies, fuzzy models using self-organization and vector quantization have been proposed. It is well known that these models construct fuzzy inference rules effectively representing distribution of input data, and not affected by increment of input dimensions. In this paper, we propose a destructive fuzzy modeling using neural gas network and demonstrate the validity of a proposed method by performing some numerical examples.

For the solutions of linear systems of equations with unsymmetric coefficient matrices, we propose an improved version of the quasi-minimal residual (IQMR) method by using the Lanczos process as a major component combining elements of numerical stability and parallel algorithm design. For Lanczos process, stability is obtained by a coupled two-term procedure that generates Lanczos vectors scaled to unit length. The algorithm is derived such that all inner products and matrixvector multiplications of a single iteration step are independent and communication time required for inner product can be overlapped efficiently with computation time. Therefore, the cost of global communication on parallel distributed memory computers can be significantly reduced. The resulting IQMR algorithm maintains the favorable properties of the Lanczos process while not increasing computational costs. The efficiency of this method is demonstrated by numerical experimental results carried out on a massively parallel distributed memory computer, the Parsytec GC/PowerPlus.

We present a scalable parallel memory architecture with a skew scheme by which permanent-concentration-free strides, if any, do not depend on the number of ways in parallel memory interleaving. The permanent-concentration is a kind of memory access conflict. With conventional skew schemes, permanent-concentration-free strides depended on the number of banks (or bank groups) in parallel memory (=number of ways in parallel memory interleaving). We analyze two kinds of cause of conflicts: permanent-concentration occurs when memory access requests concentrate in limited number of banks (or bank groups) in parallel memory, and transient-concentration, when memory access requests transiently concentrate in some banks (or bank groups) in parallel memory. We have identified permanent-concentration-free strides, which are independent of the number of banks (or bank groups) in parallel memory, by solving two concentrations separately. The strategy is to increase the size of address block of shifting address assignment to the parallel memory in order to reduce permanent-concentrations, and make the size of the buffer for each banks (or bank groups) in the parallel memory match the size of address block of shifting in order to absorb transient-concentrations. The skew scheme uses the same size of address block of shifting address assignment for memory systems for different numbers of banks (or bank groups) in parallel memory. As a result, scalability for permanent-concentration-free strides is achieved independent of the number of banks (or bank groups) in parallel memory.

In this paper, implementation of a first-order active complex filter with variable parameter using operational transconductance amplifiers (OTAs) and grounded copacitors is presented. The proposed configurations can be used as s key building block to realize high-order active complex filters with variable parameter in cascade and leapfrog configuration. Experimental results which are in good agreement with theoretical responses are also given o demonstrate the feasibility of the proposed configurations.

A novel approach to the cache coherent Multistage Interconnection Network (MIN) called the MINC (MIN with Cache control mechanism) is proposed. In the MINC, the directory is located only on the shared memory using the Reduced Hierarchical Bit-map Directory schemes (RHBDs). In the RHBD, the bit-map directory is reduced and carried in the packet header for quick multicasting without accessing the directory in each hierarchy. In order to reduce unnecessary packets caused by compacting the bit map in the RHBD, a small cache called the pruning cache is introduced in the switching element. The simulation reveals the pruning cache works most effectively when it is provided in every switching element of the first stage, and it reduces the congestion more than 50% with only 4 entries. The MINC cache control chip with 16 inputs/outputs is implemented on the LPGA (Laser Programmable Gate Array), and works with a 66 MHz clock.

Methods of automatically adjusting delay time and feedback gain in controlling chaos by delayed feedback control are proposed. These methods are based on a gradient-descent procedure minimizing the squared error between the current state and the delayed state. The method of adjusting delay time and that of adjusting feedback gain are applied to controlling chaos in numerical calculations of Rossler Equation and Duffing equation, respectively. Both methods are confirmed to be successful.

The authors previously proposed a reconfigurable architecture called the "XL-scheme" in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.

The pattern spectrum has been proposed to represent morphological size distribution of an image. However, the conventional pattern spectrum cannot extract approximate shape information from image objects spotted by noisy pixels since this is based only on opening. In this paper, a novel definition of the pattern spectrum, morphological multiresolution pattern spectrum (MPS), involving both opening and closing is proposed. MPS is capable of distinguishing details from approximate information of the image.