We propose low Rayleigh scattering Na2O-MgO-SiO2 (NMS) glass as a candidate material for low-loss optical fibers. This glass exhibits Rayleigh scattering which is only 0.4 times that of silica glass, and a theoretical evaluation suggests that it is dominated by density fluctuation. An investigation of the optical properties of NMS glass reveals that a minimum loss of 0.06 dB/km is expected at a wavelength of 1.6 µm and that the zero-material dispersion wavelength is found in the 1.5 µm band. To establish the waveguide structure, we evaluated the feasibility of using F-doped NMS (NMS-F) glass as a cladding layer for an NMS core and found that it is suitable because it exhibits low relative scattering (e.g. 0.7) and is versatile in terms of viscosity matching. We also describe an attempt to draw optical fibers using the double crucible technique.

This paper describes a new approach to the scheduling problem that assigns tasks of a parallel program described as a task graph onto parallel machines. The approach handles interprocessor communication and heterogeneity, based on using both the theoretical results developed so far and a lookahead scheduling strategy. The experimental results on randomly generated task graphs demonstrate the effectiveness of this scheduling heuristic.

A new method to obtain the coefficients of Daubechies's scaling functions is given, in which it is not necessary to find the complex zeros of polynomials. Consequently it becomes easier to obtain the coefficients of arbitrary order from 2 to 40 with high accuracy.

RF integration, until recently the integration of active devices in conventional architectures suitable for discrete-component circuits, is now turning into full-integration based on new architectures developed specifically for an LSI technology. This paper reviews some of the key existing and emerging circuit techniques and discusses the serious problem of crosstalk. In order to develop miniature and low power RF transceivers, direct-conversion and monolithic VCO's will be further studied. Silicon bipolar technology will still be playing major role beyond the year 2,000, and CMOS will also be used in certain applications.

In this paper, we propose a handoff scheme with two-level priority for the reservation of handoff request calls in mobile cellular radio systems. We assume two types of mobile subscribers with different distributions of moving speed, that is, users with low average moving speed (e.g., pedestrians) and high average moving speed (e.g., people in moving cars). A fixed number of channels in each cell are reserved exclusively for handoff request calls. Out of these number of channels, some are reserved exclusively for the high speed handoff request calls. The remaining channels are shared by both the originating and handoff request calls. In the proposed scheme, both kinds of handoff request calls make their own queues. The system is modeled by a three-dimensional Markov chain. We apply the Successive Over-Relaxation (SOR) method to obtain the equilibrium state probabilities. Blocking probabilities of calls, forced termination probabilities and average queue length of handoff calls of each type are evaluated. We can make the forced termination probabilities of handoff request calls smaller than the blocking probability of originating calls. Moreover, we can make the forced termination probability of high speed handoff request calls smaller than that of the low speed ones. Necessary queue size for the two kinds of handoff request calls are also estimated.

We demonstrate highly quick response and long distance distributed oil sensors using a newly developed eccentric core fiber (ECF). This distributed oil sensor,based on an interaction between measurand oil and evanescent-wave from the ECF, has achieved as short as 4 minutes response time by using an improved coating material and a sensing length over 17 km at a signal wavelength of 1310 nm. The observed sensitivity characteristics coincide with the calculations of the evanescent power outside the cladding and it is shown that the sensitivity can be well estimated from the amount of the outer cladding component of the evanescent power.

The multiple registration schemes (MRSs) proposed here are classified into 3 cases by combining five registration schemes which are power up registration scheme (PURS), power down registration scheme (PDRS), zone based registration scheme (ZBRS), distance based registration scheme (DBRS), and implicit registration scheme (IRS) as follows: the first is MRS1 which covers PURS, PDRS, and ZBRS; the second is MRS2 which covers PURS, PDRS, and DBRS; the third is MRS3 which covers PURS, PDRS, IRS, and DBRS. The three proposed schemes are compared each other by analyzing their combined signaling traffic of paging and registration with considering various parameters of a mobile station behavior (unencumbered call duration, power up and down rate, velocity, etc.). Also, we derive allowable location areas from which the optimal location area is obtained. Numerical results show that MRS3 yields better performance than ZBRS, DBRS, MRS1, and MRS2 in most cases of a mobile station behavior, and it has an advantage of distributing the load of signaling traffic into every cell, which is important in personal communication system.

A new memory cell arrangement for a gigabit-scale NAND DRAM is proposed. Although the conventional NAND DRAM in which memory cells are connected in series realizes the small die size, it faces a crucial array noise problem in the 1 gigabit generation and beyond because of its inherent noise of the open bitline arrangement. By introducing the new cell arrangement to a NAND DRAM, the folded bitline scheme is realized, resulting in good noise immunity. The basic operation of the proposed folded bitline scheme was successfully verified using the 64 kbit test chip. The die size of the proposed NAND DRAM with the folded bitline scheme (F-NAND DRAM) at the 1 Gbit generation is reduced to 63% of that of the conventional 1 Gbit DRAM with the folded bitline scheme, assuming the bitlines and the wordlines are fabricated with the same pitch. The new 4/4 bitline grouping scheme in which cell data are read out to four neighboring bitlines is also introduced to reduce the bitline-to-bitline coupling noise to half of that of the conventional folded bitline scheme. The array noise of the proposed F-NAND DRAM with the 4/4 bitline grouping scheme at 1 Gbit generation is reduced to 10% of the read-out signal, while that of the conventional NAND DRAM with open bitline scheme is 29%, and that of the conventional DRAM with the folded bitline scheme is 22%.

In this paper, in order to achieve the low power consumption of programmable divider in a PLL frequency synthesizer, we propose a new prescaler method for low power consumption. A fixed prescaler is inserted in front of the (N +1/2) programmable divider which is designed based on the new principle. The divider ratio in the loop does not vary at all even if such a prescaler is utilized. Then the permissible delay periods of a programmable divider can be extended to two times as long as the conventional method, and the low power consumption and low cost in a PLL frequency synthesizer have been achieved.

In this paper we present an algorithm to solve an as-yet untreated knapsack problem, the Multidimensional Multiple-choice Knapsack Problem (MMKP). Since our specific application occurs in the real-time domain, a solution for the MMKP with a small upper bound on the runtime is desirable. Thus, the Lagrange multiplier method is chosen, and a heuristic with a worst-case runtime behavior better than O(n2m) is developed, n being the number of elements and m the number of dimensions. Extensive testing against an exact algorithm based on partial enumeration is used to establish the accuracy and efficiency of the heuristic.

We consider single machine problems involving both specific and generalized due dates simultaneously. We show that a polynomial time algorithm exists for the problem of minimizing max {Lmax, LHmax}, where Lmax and LHmax are the maximum lateness induced by specific and generalized due dates, respectively. We also show that a simple efficient algorithm exists for the problem of minimizing the maximum lateness induced by due dates which are natural generalization of both specific and generalized due dates. In addition to the algorithmic results above, we show that the problems of minimizing max {LHmax, -Lmin} and max{Lmax, -LHmin} are NP-hard in the strong sense, where Lmin and LHmin are the minimum lateness induced by specific and generalized due dates, respectively.

The parasitic bipolar effect in a 200-V-class thin-film SOI power MOSFET fabricated using the silicon wafer direct bonding wafer was investigated by electrical measurement, two-dimensional process simulation, emission microscopy, and 2-dimensional thermal analysis. It degraded the breakdown voltage of the thin-film SOI power MOSFET and was caused by the increase in the sheet resistance of the body contact region. Photo emission analysis indicated that excess holes recombined in the n+-source region.

In this paper, algorithms for resource allocation in an ATM node that serves heterogeneous traffic sources subject to varying Quality of Service (QoS) requirements are proposed. The node can be either a switch port or a multiplexer. Each connection is first individually treated as logical queue. Quick and efficient algorithms allocating service rate and buffer space to each connection based on traffic characteristics and QoS requirement are developed. In order to improve link and buffer utilization, the aggregate traffic is next replaced by an appropriately parameterized new traffic source that still preserves the key characteristics of the aggregate traffic. The most stringest QoS requirement among all connections is selected to be the QoS target of the new traffic source to assure that QoS of each individual connection is satisfied. Resource allocation for the aggregate traffic is determined based on the traffic parameters and QoS target of the new source. Each individually determined service rate and buffer space can be used in cell transmission scheduling and selective cell discarding. In other words, resource allocation together with two related side problems: cell transmission and cell discarding, are treated in this paper in an integrated and efficient manner. The resource allocation algorithms proposed in this paper can also be used to support Call Admission Control (CAC) in ATM networks.

This paper studies stabilization of timed discrete event systems with forcible events. We present an algorithm for computing the region of weak attraction for legal states.

This paper describes the design and evaluation of fully scannable embedded memory arrays. A memory array, such as a register file, is made scannable by adding a small auxiliary circuit including a counter and multiplexers. Plural memory arrays can be chained into a single scan path along with ordinary flip-flops. Detailed configuration and implementation of the scannable CMOS and bipolar LCML register file macros are discussed. The overhead ratio of the CMOS register file macro with 16-word by 16-bit results in an 8.6% transistor count and a 6.4% die area. The access time overhaead is 7.8% and the set-up time increases by about 50ps. Bipolar LCML register file macros have been applied to gate array LSIs which have successfully achieved average stuck-at fault coverage of 99.2%.

This paper describes what happens when the silicon layer is extremely thinned. The discussion shows that quantum mechanical short-channel effects impose limits on the down-scaling of MOSFET/SOI devices. However, thinning the silicon layer should bring new possibilities such as mobility enhancement, velocity overshoot enhancement, suppression of band-to-band tunneling, suppression of impact ionization and so on. Furthermore, the non-stationary energy transport in extremely miniaturized ultra-thin MOSFET/SOI devices is also addressed from the viewpoint of hot-carrier immunity. Related device physics are also discussed in order to consider the design methodology for contemporary MOSFET/SOI devices and new device applications for the future.

Periodic solutions of slow-fast systems called "canards," "ducks," or "lost solutions" are examined in a second order autonomous system. A characteristic feature of the canard is that the solution very slowly moves along the negative resistance of the slow curve. This feature comes from that the solution moves on or very close to a curve which is called slow manifolds or "rivers." To say reversely, solutions which move very close to the river are canards, this gives a heuristic definition of the canard. In this paper, the generation mechanism of the canard is examined using a piecewise linear system in which the cubic function is replaced by piecewise linear functions with three or four segments. Firstly, we pick out the rough characteristic feature of the vector field of the original nonlinear system with the cubic function. Then, using a piecewise linear model with three segments, it is shown that the slow manifold corresponding to the less eigenvalue of two positive real ones is the river in the segment which has the negative resistance. However, it is also shown that canards are never generated in the three segments piecewise linear model because of the existence of the "nodal type" invariant manifolds in the segment. In order to generate the canard, we propose a four segments piecewise linear model in which the property of the equilibrium point is an unstable focus.

In the information engineering learning environment, there may be more than one solution to any given problem. We have developed CAMELOT using the Nominal Group Technique for group problem solving. This paper describes the collaborative learning system on the Internet using discussion model, the effectiveness of collaborative learning in modeling the entity-relationship diagram within the field of information engineering, and how to apply AI technologies such as rule-based reasoning and case-based reasoning to the pedagogical strategy. By using CAMELOT, each learner learns how to analyze through case studies and how to collaborate with his or her group in problem solving. As a result. We have found evidence for the effectiveness of collaborative learning, such as getting a deeper understanding by using CAMELOT than by individual learning, because they can reach better solutions through discussion, tips from other learners, examination of one another's individual solutions, and understanding alternative solutions using case-based reasoning.

In this paper, we analyze the multiple access interference of a variable processing gain DS/CDMA system and define discrete partial crosscorrelation functions. We also evaluate the bit error rate of the system using Gaussian approximation and bounding technique. Three kinds of spreading codes (long, short, and random codes) are considered in the analysis of the system. It is shown that the bit error rate of a user is not relevant to the processing gain of interfering users: it is relevant only to the processing gain of the user, transmitted powers, PN sequences, and spreading codes. The performance of short codes turns out to be better than that of long and random codes as in other systems.

High-end graphic systems with 3 million pixels require 8-bit D/A converters with more than 300-MS/s conversion rate. Furthermore, D/A converters need to operate with low supply voltage when they are integrated with large-scale digital circuits on a harf-micron CMOS process. This paper describes a 350-MS/s 8-bit CMOS D/A converter with 3.3-V power supply. A current source circuit with a delayed driving scheme is developed. This driving scheme reduces a fluctuation of internal node voltage of the current source circuit and high-speed swiching is realized. In addition to this driving scheme, two stages of latches are inserted into matrix decoder for reducing glitch energy and for enhancing decoding speed. The D/A converter is fabricated in a 0.5-µm CMOS process with single poly-silicon layer and double aluminum layers. Its settling time is less than 2.4 ns and it successfully operates at 350 MS/s.