A novel two-dimensional (2D) beam scanning antenna array using composite right/left-handed (CRLH) leaky-wave antennas (LWAs) is proposed. The antenna array consists of a set of CRLH LWAs and a Butler matrix (BM) feeding network. The direction of the beam can be scanned two-dimensionally in one plane by changing frequency and in the other plane by switching the input ports of the BM. A four-element antenna array in the microstrip line configuration operating at 10.5 GHz is designed with the assistance of full-wave simulations based on the method of moment (MoM) and the finite-element method (FEM). The antenna array is fabricated and radiation characteristics are measured. The wide range 2D beam scanning operation with the angle from -30 deg to +25 deg in one plane by sweeping frequency from 10.25 GHz to 10.7 GHz and with four discrete angles of -46 deg, -15 deg, +10 deg, and +35 deg in the other plane by switching the input port is achieved.

This paper presents the design, fabrication and characterization of a low actuation voltage capacitive shunt RF-MEMS switch for microwave and millimeter-wave applications based on a corrugated electrostatic actuated bridge suspended over a concave structure of coplanar waveguide (CPW), with sputtered nickel as the structural material for the bridge and gold for CPW line, fabricated on high-resistivity silicon (HRS) substrate using IC compatible processes for modular integration in a communication devices. The residual stress is very low because having both ends corrugated structure of the bridge in concave structure. The residual stress is calculated about 3-15 MPa in corrugated bridge and 30 MPa in flat bridge. The corrugated bridge of the concave structure requires lower actuation voltages 20-80 V than 50-100 V of the flat bridge of the planar structure in 0.3 to 1.0 µm thick Ni capacitive shunt RF-MEMS switch, in insertion loss 1.0 dB, return loss 12 dB, power loss 10 dB and isolation 28 dB from 0.5 up to 40 GHz. The residual stress of the bridge material and structure is critical to lower the actuation voltage.

We propose a Fault-Tolerant Object Group framework that provides group management and fault-tolerance services for consistency maintenance and state transparency as well. Through a virtual home-network simulation, we validate that the FTOG framework supports both of the reliability and the stability of the distributed home-network systems.

We propose a simple initial frame timing acquisition algorithm for cellular OFDMA systems. The proposed algorithm utilizes the 9 dB boost in preamble power set by the IEEE 802.16e standard. Simulation results show that the proposed algorithm succeeds in acquiring the starting point of a frame under not only single cell but also multi-cell environments, while the conventional autocorrelation-based method fails under multi-cell environment.

Multiple-access interference (MAI) limits the bit error rate (BER) performance of CDMA uplink transmission. In this paper, we propose a generalized chip-interleaved CDMA with 2-dimensional (2D) spreading using orthogonal variable spreading factor (OVSF) codes to minimize the MAI effects and achieve the maximum available time- and frequency-domain diversity gains. We present the code assignment for 2D spreading to provide users with flexible multi-rate data transmission. A computer simulation shows that by the joint use of 2D OVSF spreading and chip-interleaving, MAI-free transmission is possible for the quasi-synchronous DS- or MC-CDMA uplink, and hence the single-user frequency-domain equalization based on the MMSE criterion can be applied for signal detection. The BER performance in a time- and frequency-selective fading multiuser channel is theoretically analyzed and evaluated by both numerical computation and computer simulation.

This paper proposes a new microstrip stepped-impedance resonator (SIR) used for bandpass filters with reduced size and improved stopband characteristics. A comprehensive treatment of both ends of the resonator with loaded triangular and rectangular microstrips is described. The design concept is demonstrated by two filter examples including four-resonator parallel-coupled Chebyshev bandpass and compact four-resonator cross-coupled elliptic-type filters. These filters are not only compact size due to the slow-wave effect, but also have a wider upper stopband resulting from the resonator bandstop characteristic. The filter designs are described in details. The simulated and experimental results are demonstrated and discussed.

In this letter, efficient two-dimensional (2-D) fast algorithms for realizations of 88 forward and inverse integer transforms in H.264/AVC fidelity range extensions (FRExt) are proposed. Based on matrix factorizations with Kronecker product and direct sum operations, efficient fast 2-D 88 forward and inverse integer transforms can be derived from the one-dimensional (1-D) fast 88 forward and inverse integer transforms through matrix operations. The proposed fast 2-D 88 forward and inverse integer transform designs don't require transpose memory in hardware realizations. The fast 2-D 88 integer transforms require fewer latency delays and provide a larger throughput rate than the row-column based method. With regular modularity, the proposed fast algorithms are suitable for VLSI implementations to achieve H.264/AVC FRExt high-profile signal processing.

This paper presents a scheme for accurately detecting the number of incident waves arriving at array antennas. The array antenna and MIMO techniques are developing as 4th generation mobile communication systems and wireless LAN technologies, and the accurate estimation of the propagation environment is becoming more important. This paper emphasizes the accurate detection of the number of incident waves; one of the important characteristics in multidirectional communication. There are some recent papers on accurate detection but they have problems of estimation accuracy or computational cost in severe environment like low SNR, small number of snapshots or waves with close angles. Hence, AIC and MDL methods based on statistics and information theory are still often used. In this paper, we propose an accurate estimation method of the number of arrival signals using the orthogonality of subspaces derived from preliminary estimation of signal subspace. The proposed method accurately estimates the number of signals also in severe environments where AIC and MDL methods can hardly estimate. We evaluate the performance of these methods through some computer simulation and experiments in anechoic chamber.

In this paper, we present preliminary work on recognizing affect from a Korean textual document by using a manually built affect lexicon and adopting natural language processing tools. A manually built affect lexicon is constructed in order to be able to detect various emotional expressions, and its entries consist of emotion vectors. The natural language processing tools analyze an input document to enhance the accuracy of our affect recognizer. The performance of our affect recognizer is evaluated through automatic classification of song lyrics according to moods.

In this paper, we propose a methodology for calculating on-chip temperature gradient and leakage power distributions. It considers the interdependence between leakage power and local temperature using a general circuit simulator as a differential equation solver. The proposed methodology can be utilized in the early stages of the design cycle as well as in the final verification phase. Simulation results proved that consideration of the temperature dependence of the leakage power is critically important for achieving reliable physical designs since the conventional temperature analysis that ignores the interdependence underestimates leakage power considerably and may overlook potential thermal runaway.

This paper presents a structural approach for synthesizing arbitrary multi-output multi-stage static CMOS circuits at the transistor level, targeting the reduction of transistor counts. To make the problem tractable, the solution space is restricted to the circuit structures which can be obtained by performing algebraic transformations on an arbitrary prime-and-irredundant two-level circuit. The proposed algorithm is guaranteed to find the optimal solution within the solution space. The circuit structures are implicitly enumerated via structural transformations on a single graph structure, then a dynamic-programming based algorithm efficiently finds the minimum solution among them. Experimental results on a benchmark suite targeting standard cell implementations demonstrate the feasibility and effectiveness of the proposed approach. We also demonstrated the efficiency of the proposed algorithm by a numerical analysis on randomly-generated problems.

A unified representation for various kinds of speculations and global scheduling algorithms is presented. After introducing several types of local and global speculations, reviewing our conventional method called conditional vector-based list scheduling, and discussing some of its limitations, we introduce the unique notion of generalized condition vectors (GCVs), which can represent most varieties of speculations and multiple branches as a single vector. The unification of parallel branches and partially unresolved nested conditional branches is discussed. Then, a scheduling algorithm using GCVs is proposed. Experimental results show the effectiveness of the GCV-based scheduling method.

High-level synthesis is a novel method to generate a RT-level hardware description automatically from a high-level language such as C, and is used at recent digital circuit design. Floating-point to fixed-point conversion with bit-length optimization is one of the key issues for the area and speed optimization in high-level synthesis. However, the conversion task is a rather tedious work for designers. This paper introduces automatic bit-length optimization method on floating-point to fixed-point conversion for high-level synthesis. The method estimates computational errors statistically, and formalizes an optimization problem as a non-linear problem. The application of NLP technique improves the balancing between computational accuracy and total hardware cost. Various constraints such as unit sharing, maximum bit-length of function units can be modeled easily, too. Experimental result shows that our method is fast compared with typical one, and reduces the hardware area.

An even harmonic quadrature mixer (EH-QMIX) with a balanced configuration is proposed for a direct conversion receiver. The unit even harmonic mixer (EHMIX) used for I/Q paths consists of two anti parallel diode pairs (APDPs) and a pair of diplexers. When the second harmonic of LO (2LO) from the LO section is applied to the LO port as a spurious component, a conventional single-ended EHMIX using APDP converts the 2LO leakage from the LO section into the baseband and the d.c. offset and the self-detected LO noise arise at the baseband degrade the sensitivity. This proposed balanced EHMIX configuration can cancel out the 2LO leakage in itself. Therefore, the d.c. offset and the LO noise are significantly suppressed and the degradation of the sensitivity can be avoided. The suppression characteristic of the d.c. offset and the LO noise are verified by the simulation and the measurements. By using this balanced configuration, the fabricated EH-QMIX achieves wider frequency band characteristic than that of the single-ended EH-QMIX, and it shows 20% relative bandwidth at L-band.

This paper presents novel phase-continuous frequency hopping (FH) control for a direct frequency synthesizer (DFS) using a quadrature mixer driven by two direct digital synthesizers (DDSs). To achieve wideband FH in both of the lower and the upper sidebands of a local frequency in a quadrature mixer, the proposed DFS decreases or increases the phase of DDS output signals corresponding to frequency offset from a local frequency of the quadrature mixer. To realize phase decrement, the proposed method adds a complement number in a phase accumulator of a DDS, while a conventional DDS does not use phase decrement but uses a switchable combiner. In addition, as the phase accumulator output changes continuously by summing phase increment, the proposed method always assures phase continuity of a DFS output signal, which ends up suppressing sidelobe level of frequency hopped signals. The calculation and measurement results indicate that a sidelobe of a signal spectrum using the proposed phase continuous method is approximately 10 dB better than that using a conventional phase discontinuous method.

We derived explicit formulas for evaluating the error vector magnitude (EVM) from the amplitude distortion (AM-AM) and phase distortion (AM-PM) of power amplifiers (PAs) in orthogonal frequency-division multiplexing (OFDM) systems, such as the IEEE 802.11a/g wireless local area networks (WLANs) standards. We demonstrated that the developed formulas allowed EVM simulation of a memoryless PA using only a single-tone response (i.e. without OFDM modulation and demodulation), thus enabling us to easily simulate the EVM using a harmonic-balance (HB) simulator. This HB simulation technique reduced the processing time required to simulate the EVM of a PA for the IEEE 802.11a standard by a factor of ten compared to a system-level (SL) simulation. We also demonstrated that the measured EVM of a PA module for the IEEE 802.11g could accurately be predicted by applying the measured static AM-AM and AM-PM characteristics to the derived formulas.

This paper represents a cycle-based logic simulation method using an LUT cascade emulator, where an LUT cascade consists of multiple-output LUTs (cells) connected in series. The LUT cascade emulator is an architecture that emulates LUT cascades. It has a control part, a memory for logic, and registers. It connects the memory to registers through a programmable interconnection circuit, and evaluates the given circuit stored in the memory. The LUT cascade emulator runs on an ordinary PC. This paper also compares the method with a Levelized Compiled Code (LCC) simulator and a simulator using a Quasi-Reduced Multi-valued Decision Diagram (QRMDD). Our simulator is 3.5 to 10.6 times faster than the LCC, and 1.1 to 3.9 times faster than the one using a QRMDD. The simulation setup time is 2.0 to 9.8 times shorter than the LCC. The necessary amount of memory is 1/1.8 to 1/5.5 of the one using a QRMDD.

This paper presents an architecture and a synthesis method for compact numerical function generators (NFGs) for trigonometric, logarithmic, square root, reciprocal, and combinations of these functions. Our NFG partitions a given domain of the function into non-uniform segments using an LUT cascade, and approximates the given function by a quadratic polynomial for each segment. Thus, we can implement fast and compact NFGs for a wide range of functions. Experimental results show that: 1) our NFGs require, on average, only 4% of the memory needed by NFGs based on the linear approximation with non-uniform segmentation; 2) our NFG for 2x-1 requires only 22% of the memory needed by the NFG based on a 5th-order approximation with uniform segmentation; and 3) our NFGs achieve about 70% of the throughput of the existing table-based NFGs using only a few percent of the memory. Thus, our NFGs can be implemented with more compact FPGAs than needed for the existing NFGs. Our automatic synthesis system generates such compact NFGs quickly.

This paper proposes a method to determine a single frequency for interconnect RL extraction. Resistance and inductance of interconnects depend on frequency, and hence the extraction frequency strongly affects the modeling accuracy of interconnects. The proposed method determines an extraction frequency based on the transfer characteristic of interconnects. By choosing the frequency where the transfer characteristic becomes maximum, the extracted RL values achieve the accurate modeling of the waveform. Experimental results show that the proposed method provides accurate transition waveforms over various interconnect topologies.

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In MTCMOS circuit, voltage on virtual ground fluctuates due to a discharge current of a logic cell. This event affects to the cell delay and makes static timing analysis (STA) difficult. In this paper, we propose a delay modeling and static STA methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. This technique enables to calculate the cell delay considering the delay increase by the voltage fluctuation of virtual ground line. Experimental results show that the proposed methodology enables to estimate the cell delay and the critical path delay within 8% errors compared with SPICE simulation.