We propose a simple initial frame timing acquisition algorithm for cellular OFDMA systems. The proposed algorithm utilizes the 9 dB boost in preamble power set by the IEEE 802.16e standard. Simulation results show that the proposed algorithm succeeds in acquiring the starting point of a frame under not only single cell but also multi-cell environments, while the conventional autocorrelation-based method fails under multi-cell environment.

This paper describes a new method for the simulation environment for a custom processor. It is generally very hard to develop an accurate simulator for a custom processor rapidly, even if simple instruction-set-level simulator (ISS). The proposed method uses a field-programmable-gate-array emulator with a PCI interface and debugging GUI software on a PC. Since the emulator implements the processor design at the register-transfer or net-list level, the emulation results are almost the same as the results obtained with the actual processor. To support rich debugging functions like those provided by the conventional software simulator, we use a debugging buffer and break-control circuits. Experimental results show that a simulator constructed by the proposed method can be constructed within several hours and that it can break the processor operation at any specified point and observe the internal signals when the emulated system is running at 1-30 MHz. The accuracy of the constructed simulator is the same as that of RTL simulation and much higher than that of software ISS simulation. We show that we can provide a fast, accurate, and useful simulator for any processor design specified at the register-transfer level.

This paper proposes a new microstrip stepped-impedance resonator (SIR) used for bandpass filters with reduced size and improved stopband characteristics. A comprehensive treatment of both ends of the resonator with loaded triangular and rectangular microstrips is described. The design concept is demonstrated by two filter examples including four-resonator parallel-coupled Chebyshev bandpass and compact four-resonator cross-coupled elliptic-type filters. These filters are not only compact size due to the slow-wave effect, but also have a wider upper stopband resulting from the resonator bandstop characteristic. The filter designs are described in details. The simulated and experimental results are demonstrated and discussed.

This paper presents the analogical conception of Chomsky normal form and Greibach normal form for linear, monadic context-free tree grammars (LM-CFTGs). LM-CFTGs generate the same class of languages as four well-known mildly context-sensitive grammars. It will be shown that any LM-CFTG can be transformed into equivalent ones in both normal forms. As Chomsky normal form and Greibach normal form for context-free grammars (CFGs) play a very important role in the study of formal properties of CFGs, it is expected that the Chomsky-like normal form and the Greibach-like normal form for LM-CFTGs will provide deeper analyses of the class of languages generated by mildly context-sensitive grammars.

This paper presents a formal design of arithmetic circuits using an arithmetic description language called ARITH. The key idea in ARITH is to describe arithmetic algorithms directly with high-level mathematical objects (i.e., number representation systems and arithmetic operations/formulae). Using ARITH, we can provide formal description of arithmetic algorithms including those using unconventional number systems. In addition, the described arithmetic algorithms can be formally verified by equivalence checking with formula manipulations. The verified ARITH descriptions are easily translated into the equivalent HDL descriptions. In this paper, we also present an application of ARITH to an arithmetic module generator, which supports a variety of hardware algorithms for 2-operand adders, multi-operand adders, multipliers, constant-coefficient multipliers and multiply accumulators. The language processing system of ARITH incorporated in the generator verifies the correctness of ARITH descriptions in a formal method. As a result, we can obtain highly-reliable arithmetic modules whose functions are completely verified at the algorithm level.

A new 4B5B block inversion coding is proposed for dc-balanced transmission in high-speed optical parallel links. An 8-bit byte is partitioned into two 4-bit data and converted to two 5-bit blocks by an inversion encoding. The proposed coding greatly reduces circuit complexity with the minimum latency overhead of one clock for the encoder and none for the decoder. The maximum run length is 11.

This letter presents an efficient Signed-Power-of-Two (SPT) term allocation for filter coefficients in order to improve the BER characteristics of digital communication systems. The performance of the present allocation is evaluated by BER characteristics through digital modulation simulations and FPGA-based digital implementation.

This paper presents a family of rate-one quasi-orthogonal space-time block codes (QO-STBCs) for any number of transmit antennas. Full diversity of the proposed QO-STBCs is achieved via the use of constellation rotation. When the number of transmit antennas is even, these codes are delay "optimal." This property along with the quasi-orthogonality one allows the codes to have low decoding complexity. Besides, by applying lookup tables into the detection methods presented in [1] and generalizing them, two low-complexity maximum-likelihood (ML) decoders for the proposed QO-STBCs and for other existing QO-STBCs, called PMLD and QMLD, are obtained. Simulation results are provided to verify the bit error rate (BER) performances and complexities of both the proposed QO-STBCs and the proposed decoders.

A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 µm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25), a clock frequency of 266 MHz can be achieved.

Organic field-effect transistors (OFETs) based on a composite with the same thiophene backbone were fabricated by spin coating using an annealing solution of poly(3-hexylthiophene) (PAT6) and α, ω-dihexylsexithiophene (DH-6T). The morphology of grains on the non-octadecyltrichlorosilane (OTS) treated and OTS treated gate insulators is granular and tube-like, respectively. The different morphologies of the OFETs with non-OTS treated and OTS-treated gate insulators result in the improvement of field-effect mobility. In the case of poly(ethylene naphthalate) substrate, an OFET with an 89 wt% DH-6T composite corresponding to two molecules of DH-6T per hexylthiophene repeating unit had a carrier mobility of 0.019 cm2/Vs.

It has been shown that the maskless dye-diffusion technique is applicable to a conjugated polymer poly(9,9-dioctylfluorene). The introduction of Coumarin 6 and Nile red results in green and white emission, with the increased onset voltage for the both cases. It has also been confirmed that the heat treatment effect during the maskless dye diffusion technique results in not the increase but the decrease of the onset voltage, indicating that the dye plays a role of carrier trap in the polymer.

We derived explicit formulas for evaluating the error vector magnitude (EVM) from the amplitude distortion (AM-AM) and phase distortion (AM-PM) of power amplifiers (PAs) in orthogonal frequency-division multiplexing (OFDM) systems, such as the IEEE 802.11a/g wireless local area networks (WLANs) standards. We demonstrated that the developed formulas allowed EVM simulation of a memoryless PA using only a single-tone response (i.e. without OFDM modulation and demodulation), thus enabling us to easily simulate the EVM using a harmonic-balance (HB) simulator. This HB simulation technique reduced the processing time required to simulate the EVM of a PA for the IEEE 802.11a standard by a factor of ten compared to a system-level (SL) simulation. We also demonstrated that the measured EVM of a PA module for the IEEE 802.11g could accurately be predicted by applying the measured static AM-AM and AM-PM characteristics to the derived formulas.

We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.

A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By the design concept using this technology, a 30% reduction in wiring delay is obtained for critical path. A 5% reduction in chip size is also obtained as the effect of decrease in repeater number for a typical high-performance multi-processing unit (MPU) in 0.13 µm generation. An example for performance enhancement in an actual product of graphic MPU chip is also demonstrated.

This paper proposes a network design scheme for Virtual Private Network (VPN) services. Traditionally, network design to compute required amount of resource is based on static point-to-point resource demand. This scheme is effective for traditional private line services. However, since VPN services allow multi-site connectivity for customers, it may not be appropriate to design a network based on static point-to-point resource demand. In particular, this scheme is not effective when the traffic pattern changes over time. Therefore, network design for VPN services introduces a new challenge in order to comply with traffic flexibility. There are conventional studies tackling this issue. In those studies, by defining a resource demand model considering flexibility, and designing the network based on this model, amount of resource required can be computed. However, there are some deficiencies in those studies. This paper proposes a new network design scheme, consisting of two components. The first one is a new resource demand model, created by extending conventional resource demand models, that can specify resource demand more precisely. The second one is a new network design algorithm for this resource demand model. Simulations are conducted to evaluate the performance of the proposed network design scheme, and the results show significant performance improvement against conventional schemes. In addition, deployment considerations of the proposed scheme are analyzed.

A novel pitch-synchronous auditory-based feature extraction method for robust automatic speech recognition (ASR) is proposed. A pitch-synchronous zero-crossing peak-amplitude (PS-ZCPA)-based feature extraction method was proposed previously and it showed improved performances except when modulation enhancement was integrated with Wiener filter (WF)-based noise reduction and auditory masking. However, since zero-crossing is not an auditory event, we propose a new pitch-synchronous peak-amplitude (PS-PA)-based method to render the feature extractor of ASR more auditory-like. We also examine the effects of WF-based noise reduction, modulation enhancement, and auditory masking in the proposed PS-PA method using the Aurora-2J database. The experimental results show superiority of the proposed method over the PS-ZCPA and other conventional methods. Furthermore, the problem due to the reconstruction of zero-crossings from a modulated envelope is eliminated. The experimental results also show the superiority of PS over PA in terms of the robustness of ASR, though PS and PA lead to significant improvement when applied together.

Fundamental limitation on assisting a write margin (WRTM) by reducing the cell terminal bias (VDDM) has been made clear for the first time and the new cell terminal biasing scheme featuring a differential VDDM (Diff-VDDM) control has been proposed to address the issues which the conventional schemes proposed so far can not overcome [1]-[5]. Since Diff-VDDM biasing scheme can meet the both of the requirements simultaneously of 1) reducing drivability for the PMOS load transistor on the "Low" written bit-line (BL) side, and 2) increasing drivability for the other side PMOS for a write recovery, it can provide a lower minimum operating voltage (Vdd_min) for the write operation even if considering a sufficiently-large random threshold voltage (Vth) variations. The following points have been shown based on an actual 65 nm CMOS device variation data and the implemented layout data that 1) Vdd_min for the write operation can be lowered from Vdd=1.1 V down to 0.8 V when considering a 4-sigma (σ) variation, 2) the write recovery time can be reduced by 92% and 70% that for the conventional schemes [1],[2] at Vdd=0.7 V and 1.0 V, respectively, and 3) WRTM defined by the percentage (%) of the required (BL pull-down level/Vdd) to flip the cell nodes for the write operation can be relaxed by 2.6-fold and 1.4-fold that for the conventional schemes [1],[2] at Vdd=0.75 V and 1.0 V, respectively. As an actual implementation in a 65 nm CMOS, a 32-kbit single-port SRAM macro design and the measured butterfly curves have been demonstrated.

For broadband wireless networks based on OFDM (Orthogonal Frequency Division Multiplexing), an FRF (Frequency Reuse Factor) of 1 has been highly desirable for more improved channel throughput. However, due to the limited power budget of MSs (Mobile Stations) or the increase in ICI (Inter-Cell Interference), a required QoS (Quality of Service) may not be maintained. This paper addresses an optimal LCRTD (Loading Control based on Region-Time Division) over multi-cell environments for an efficient uplink QoS control. In the LCRTD scheme, a cell is divided into several regions by utilizing an optimization approach under QoS constraints, and users in each region are allowed to send their data at the allocated time slots. In the simulation, it is demonstrated that a decrease of 26% in the transmit power can be obtained.

This paper introduces a block based motion estimation algorithm based on projection with adaptive window size selection. The blocks cannot match well if their corresponding 1D projection does not match well, with this as foundation 2D block matching problem is translated to a simpler 1D matching, which eliminates majority of potential pixel participation. This projection method is combined with adaptive window size selection in which, appropriate search window for each block is determined on the basis of motion vectors and prediction errors obtained for the previous block, which makes this novel method several times faster than exhaustive search with negligible performance degradation. Encoding QCIF size video by the proposed method results in reduction of computational complexity of motion estimation by roughly 45% and over all encoding by 23%, while maintaining image/video quality.

We propose a scheme by which Broadcast Satellite/Communication Satellite- radio frequency (BS/CS-RF) converted TV signals are transmitted over optical fiber, and also propose a simultaneous Frequency Modulation (FM) converted CATV and BS/CS-RF converted TV optical transmission system as one of its applications. To confirm the proposals, we demonstrate the simultaneous transport of FM converted CATV signals and BS/CS-RF converted TV signals over a single optical fiber. In the experiments, 40 carriers of AM-VSB CATV channels, 30 carriers of 64-QAM digital TV channels, 8 carriers of FM/TC8PSK BS-TV channels, and 12 carriers of QPSK CS-TV channels are simultaneously transmitted. For optical access network application, the practical transmission length of 15 km over 1.3 µm-zero-dispersion optical fiber can be achieved by using dispersion compensation fiber (DCF).