Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was developed. The technique can be applied to basic logic gates, full adders, multiplier units, and more complicated arithmetic logics like Conditional Carry Select (CCS) circuit. The magnitude of propagation delay time of RPL is smaller than the conventional CPL(Complementary Pass-transistor Logic), or DPL (Double Pass-transistor Logic). Low power consumption can also be achieved by reduced number of transistors and metal interconnections. Simulation and layout data also proved that RPL is advantageous over existing dual-rail logics while considering speed, power consumption and layout area.

This paper presents an O(mn log n) time algorithm for an approximate string matching problem, in which a pattern string may contain variable length don't care characters. This problem is important for searching DNA sequences or amino acid sequences.

Three techniques are proposed for reducing the time required for protocol processing: protocol data unit management using page management, assembly and disassembly of data packet header and contents in hardware, and rescheduling of protocol processing. These techniques were shown to be feasible by applying them to the TCP/IP over a fiber-distributed data interface network. The maximum communication throughput was 91.6 Mbps; the total throughput for 64 sessions was 89.6 Mbps, only 2% less than the maximum. These techniques will enable the development of more effcient video-on -demand systems.

An attenuation correction method was proposed for laser-produced plasma emission computed tomography (ECT), which is based on a relation of the attenuation coefficient and the emission coefficient in plasma. Simulation results show that the reconstructed images are dramatically improved in comparison to the reconstructions without attenuation correction.

This paper proposes fast FIR digital filter structures using the minimal number of adders. Filter coefficients are expressed with canonic signed digit (CSD) code and Hartley's technique is used to minimize the number of adders and subtractors. The proposed filters implemented as wired logic are fast because the structure having the shortest critical path is selected. Two algorithms are given to obtain such fast structures. In many examples the critical path length of the filter structures obtained using the proposed method is equal to that of the conventional CSD structures. This paper also presents a new design method of FIR filters using the mixed integer programming (MILP). Utilization of common expressions in Hartley's technique widens the CSD coefficient space. Thus the MILP may lead to better frequency responses. Superior frequency responses are actually obtained in many simulations.

The medial axis transform (MAT) is an image representation scheme. For a binary image, the MAT is defined as a set of upright maximal squares which consist of pixels of value l entirely. The MAT plays an important role in image understanding. This paper presents a parallel algorithm for computing the MAT of an n n binary image. We show that the algorithm can be performed in O(log n) time using n2/log n processors on the EREW PRAM and in O(log log n) time using n2/log log n processors on the common CRCW PRAM. We also show that the algorithm can be performed in O(n2/p2 + n) time on a p p mesh and in O(n2/p2 + (n log p)/p) time on a p2 processor hypercube (for 1 p n). The algorithm is cost optimal on the PRAMs, on the mesh (for 1 p n) and on the hypercube (for 1 p n/log n).

2D (two-dimensional) convolution is a basic operation in image processing and requires intensive computation. Although the SIMD model is considered suitable for 2D convolution, previous 2D convolution algorithms on the SIMD model assume unbounded number of PEs (Processing Elements) available, which we call unbounded case. Unbounded case could not be satisfied on real computers. In this paper, time-optimal data-parallel 2D convolution is studied on mesh-connected SIMD computers with bounded number of PEs. Because the optimal computation complexity is not difficult to achieve, the main concern of this paper is how to achieve optimal communication complexity. Firstly the lower bound computation complexity is analyzed. Then the lower bound communication complexities are analyzed under two typical data-distribution strategies: block-mapping and cyclic-mapping. Based on the analysis result, an optimal algorithm is presented under the block-mapping. The algorithm achieves the lower bound complexity both in computation and in communication.

This paper discusses a massively parallel interconnection scheme for multithreaded architecture and introduces a new class of direct interconnection networks called the hierarchical Multidimensional Directed Cycles Ensemble (hMDCE). Its suitability for massively parallel systems is discussed. The network is evolved from the Multidimensional Directed Cycles Ensemble (MDCE) network, where each node is substituted by lower-level sub-networks. The new network addresses some serious problems caused by the increasing scale of parallel systems, such as longer latency, limited throughput and high implementation cost. This paper first introduces the MDCE network and then presents and examines in detail the hierarchical MDCE network. Bisection bandwidth of hMDCE is considerably reduced from its ancestor MDCE and the network performs significantly higher throughput and lower latency under some practical implementation constraints. The gate count and delay time of the compiled circuit for the routing function are insignificant. These results reveal that the hMDCE network is an important candidate for massively parallel systems interconnection.

Nonuniform traffic can degrade the overall performance of multistage interconnection networks substantially. In this paper, this performance degradation is traced back to blocking effects that are not present under uniform traffic patterns within a network. This blocking phenomenon is not mentioned in the literature and is termed higher order Head-of-Line-blocking (HOLk-blocking) in this paper. Methods to determine the HOL-blocking order of multistage networks in order to classify the networks are presented. The performance of networks under hot-spot traffic as a function of their HOL-blocking characteristics is studied by simulation. It is shown that network bandwidth and packet delay improve under nonuniform traffics with increasing HOL-blocking order of a network.

This paper proposes new algorithms for diagnosing (detection, identification and location) baseline multistage interconnection networks (MIN) as one of the basic units in a massively parallel system. This is accomplished in the presence of single and multiple faults under a new fault model. This model referred to as the geometric fault model, considers defective crossing connections which are located between adjacent stages, internally to the MIN (therefore, a fault corresponds to a physical bridge fault between two connections). It is shown that this type of fault affects the correct geometry of the network, thus requiring a different testing approach than previous methods. Initially, an algorithm which detects the presence of bridge faults (both in the single and multiple fault cases), is presented. For a single bridge fault, the proposed algorithm locates the fault except in an unique pathological case under which it is logically impossible to differentiate between two equivalent locations of the fault (however, the switching element affected by this fault is uniquely located). The proposed algorithm requires log2 N test vectors to diagnose the MIN as fault free (where N is the number of input lines to the MIN). For fully diagnosing a single bridge fault, this algorithm requires at most 2 log2 N tests and terminates when multiple bridge faults are detected. Subsequently, an algorithm which locates all bridge faults is given. The number of required test vectors is O(N). Fault location of each bridge fault is accomplished in terms of the two lines in the bridge and the numbers of the stages between which it occurs. Illustrative examples are given.

The objective of this paper is to find a parametric representation for the vocal-tract log-area function that is directly and simply related to basic acoustic characteristics of the human vocal-tract. The importance of this representation is associated with the solution of the articulatory-to-acoustic inverse problem, where a simple mapping from the articulatory space onto the acoustic space can be very useful. The method is as follows: Firstly, given a corpus of log-area functions, a parametric model is derived following a factor analysis technique. After that, the articulatory space, defined by the parametric model, is filled with approximately uniformly distributed points, and the corresponding first three formant frequencies are calculated. These formants define an acoustic space onto which the articulatory space maps. In the next step, an independent component analysis technique is used to determine acoustic and articulatory coordinate systems whose components are as independent as possible. Finally, using singular value decomposition, acoustic and articulatory coordinate systems are rotated so that each of the first three components of the articulatory space has major influence on one, and only one, component of the acoustic space. An example showing how the proposed model can be applied to the solution of the articulatory-to-acoustic inverse problem is given at the end of the paper.

We develop a simulation environment for designing and examining a neural network model at the network level. The aim of our research is to enable researchers investigating neural network connective models to save time by being equipped with a graphical user interface and database of the network models. This environment consists of three parts: (1) the kernel of the simulation system, (2) NNDBMS (Neural Networks DataBase Management System), and (3) a system for displaying simulation results in various ways.

The effect of silicone vapour concentration on the contact failure was examined by using micro relays and motor brush-slip ring(commutator) contacts, [(CH3) 2SiO]4: D4 was used as a vapour source of silicone contamination. Because the influence of the vapour of the silicone on the contact surface can not be avoided at all times due to its gradual evaporation in the atmosphere. The contact failure caused by the silicone vapour was confirmed as formation of SiO2 on the contact surfaceby analysis of EPMA and XPS. A minimum limiting concentration level which does not affect contact reliability was found. This limiting level was 10 ppm(O.13mg/l). Validity of the limiting level was confirmed by the relationships among concentration, temperature, SiO2 film thickness and contact resistance. Furthermore, the effect of the degree of silicone polymerization on the limiting concentration was derived by an empirical formula. This silicone is found to have polymerization degree larger than D7: n=7. These results were confirmed by the contact failure data due to the silicone contamination.

The principles and design of current sense amplifiers for low-voltage MOS memories are described. The low input impedance of current sense amplifiers is explained using a simple model consisting of negative and positive resistance. A description of the model realized by a common-gate MOS amplifier employing transconductance enhancing techniques is also given. Some current sensing schemes for low-voltage ROM's and/or SRAM's are shown. For SRAM application, a current sensing scheme employing large-gain inverter-type amplifiers is proposed. A test chip including SRAM macrocells was designed and fabricated with 3.3-V 0.5-µm CMOS technology. An SRAM using current sense amplifiers was able to demonstrate that current sensing suppressed bitline delay to half that in conventional current-mirror types. The current sense amplifier had the same operating limit as the current-mirror type for low supply voltages. The measured operating limit of the STSM in this work was 1.3-V for threshold voltages of 0.55-V(n-channel) and -0.65-V(p-channel).

The characteristics of a-Si bottom-gate TFT test devices with several kinds of inorganic "quasi-black matrix," such as metal, semiconductor, and insulator, on the top were investigated for various black matrix(BM) resistivities. In the Ia-Vg characteristics, for a BM sheet resistance of about1 1012 Ω/, a high off current and large Vth shift were observed due to the back-gating effects when the BM is charged up. Accrding to the ac dynamic characteristics, there was almost no leakage due to the capacitive coupling between source and drain after 16.6 msec(one frame) when the BM sheet resistance was above 7 1013 Ω/ . It was found that hydrogenated amorphous silicon germanium(a-SiGe:H) film, which has enough optical density, with the sheet resistance above the order of 1014 Ω/ is a promising candidate for an inorganic BM on TFT array.

We report recent progress in the development of Liquid Crystal(LC) materials for the TN-TFT and ECB-TFT technologies, which require LC materials with positive and negative dielectric anisotropy, respectively. Many kinds of new LC materials have been synthesized and have been evaluated based on their fundamental physical properties. We have succeeded in identifying new LC materials, and developing new LC mixtures based on those, so that the current typical requirements of TFT-LCDs e.g. fast switching times, low power consumption, good viewing angles and wide operation temperature ranges together with high reliability can be fulfilled.

The transform coding scheme is often used for data compression of images, but the blocking effects peculiar to the scheme appear more clearly in reproduced images as a coding rate (bits/pixel) decreases. These effects can sometimes be viewed as a periodical square-grid overlaying the images. In this paper,we propose a new method for selectively measuring the above blocking effects among several types of image degradation by means of the techniques of nonlinear signal processing for spectral infomation (cepstral techniques), in order to compare the amount of blocking effects for the different coding images. First a two-component model which consists of DC and AC images, is discussed from a viewpoint of subimage-by-subimage coding, and some basic properties of cepstral information for the model are investigated. Then we show a procedure to compute the cepstral information for two-dimensional image signals taking the horizontal and vertical directions ioto account, and introduce a cepstral mean square error (CMSE) as a new measure to estimate the amount of blocking effects. The computer simulation results for some test images using different coding schemes show that the amount of blocking effects in each image can be easily measured and estimated by this method even when the blocking effects appear slightly.

This paper provides an architectural study of optical ring trunk-transmission networks using either Time Division Multiplexing (TDM) or Wavelength Division Multiplexing (WDM). A timeslot arrangement algorithm for distributed controlled TDM rings is proposed that minimizes the number of slots (wavelengths) required in bi-directional ring networks. This algorithm is applied in a straightforward manner to wavelength arrangement in WDM ring networks. The technique, characterized by timeslot (or wavelength) conversion, realizes common add/drop procedures in all Add/Drop Multiplexers (ADMs) when they are connected logically in a mesh topology. A self-healing algorithm is also proposed for network restoration. It offers good performance in terms of protection line-capacity, restoration delay, and survivability against multiple failures.

This paper proposes a fast timing recovery method with a decision feedback equalizer for baudrate sampling. The proposed method features two special techniques. The first one is for coarse estimation of the sampling phase. Internal signals of the oversampled analog-to-digital converter at different phases are directly taken out for parallel evaluation. The second technique provides fine tuning with a phase-modification stepsize which is adaptively controlled by the residual intersymbol interference. Simulation results by a full-duplex digital transmission system with a multilevel line code show superiority of the proposed method. The coarse timing estimation and the fine tuning reduce 75% and 40% of the time required by the conventional method,respectively. The overall saving in timing recovery is almost 60% over the conventional method. The proposed method could easily be extended to other applications with a decision feedback equalizer.

This paper describes a trial of evaluating the proper characteristics of multiple sound insulatain systems from their output responses contaminated by unknown background noises. The unknown parameters of sound insulation systems are first estimated on the basis of hte linear time series on an intensity scale, describing functionally the input-output relation of the systems. Then, their output probability distributions are predicted when an arbitrary input noise passes through these insulation systems.