This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

Recently, various efficient algorithms for solving combinatorial optimization problems using BDD-based set manipulation techniques have been developed. Minato proposed O-suppressed BDDs (ZBDDs) which is suitable for set manipulation, and it is utilized for various search problems. In terms of practical limits of space, however, there are still many search problems which are solved much better by using conventional branch-and-bound techniques than by using BDDs or ZBDDs, while the ability of conventional branch-and-bound approaches is limited by computation time. In this paper, an extension of APPLY operation, named APPRUNE (APply + PRUNE) operation, is proposed, which performs APPLY operation (ZBDD construction) and pruning simultaneously in order to reduce the required space for intermediate ZBDDs. As a prototype, a specific algorithm of APPRUNE operation is shown by assuming that the given condition for pruning is a threshold function, although it is expected that APPRUNE operation will be more effective if more sophisticated condition are considered. To reduce size of ZBDDs in intermediate steps, this paper also pay attention to the number of cared variables. As an application, an exact-minimization algorithm for generalized Reed-Muller expressions (GRMs) is implemented. From experimental results, it is shown that time and memory usage improved 8.8 and 3.4 times, respectively, in the best case using APPRUNE operation. Results on generating GRMs of exact-minimum number of not only product terms but also literals is also shown.

Memory Sharing Processor Array (MSPA) architecture has been developed as an effective array processing architecture for both reduced data storages and increased processor cell utilization efficiency [1]. In this paper, the MSPA design methodology is extended to the VLSI synthesis of a serial input processor array (Pa). Then, a new bit-serial input multiplier and a new data serial input matrix multiplier are derived from the new PA. These multipliers are superior to the conventional multipliers by their smaller number of logic-gate count.

A current controlled CMOS output driver was designed by using a temperature-insensitive reference current generator. It eliminates the need for overdesign of the driver transistor size to meet the delay specification at high temperature. Comparison with the conventional CMOS output driver with the same transistor size showed that the ground bounce noise was reduced by 2.5 times and the delay time was increased by 1.4 times, at 25 for 50pF load. The temperature variations of the DC pull-up and pull-down currents of the new output driver were 4% within the temperature range from -15 to 125 compared to the variations of 40 and 60% for pull-up and pull-down respectively for the conventional output driver. The temperature insensitivity of the reference current generator was achieved by multiplying two current components. one which is proportional to mobility and the other which is inversely proportional to mobility, by using a CMOS square root circuit. The temperature variation of the DC output current of the reference current generator alone was 0.77% within the entire temperature range from -15 to 125.

This paper proposes a small 1/4Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F2 size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.

High level power estimation model is indispensable to optimize architecture and programs in terms of power consumption systematically. This paper describes power analysis results of a general purpose programmable DSP using switch level and cell based power simulation. The analysis results help to know characteristics of the DSP components and to establish a power estimation model. A compensation method for the lack of intra-cell capacitance in a cell based simulation is proposed to improve the simulation accuracy within -20% of error against the measured power. We considered that the error is caused by ignoring short circuit current and is accurate enough for this level of simulation. Through a result of the power breakdown by modules of the DSP obtained by the simulation, it was found that bus power is much less than generally expected (the simulated power is less than 5% of the total), and that the data operation power dominates the chip power (up to 33%) and is strongly data dependent. The reason that the bus power is low is because both of the load capacitance and the activity are low. Some correlation between the number of input signal transitions and the power consumption is found in each of an ALU, register file, and multiplier through further investigation on the data operation modules. The correlation is worthwhile to establish a power estimation model and is eventually useful to optimize a DSP architecture and DSP programs. The importance of power estimation model is demonstrated by showing an example in which we optimize an FIR filter program based upon the analysis results and proposed a direction of architecture optimization.

A low power consumption 16-bit fixed point Digital Signal Processor (DSP) has been developed to realize a half-rate CODEC for the Personal Digital Cellular (PDC) system. Dual datapath architecture has been employed to execute multiply-accumulate (MAC) operations with a high degree of efficiency. With this architecture. 86.3% of total MAC operations in the Pitch Synchronous Innovation Code Excited Linear Prediction (PSI-CELP) program are executed in parallel, so that total instruction cycles are reduced by 23.1%. The area overhead for the dual datapath architecture is only 3.0% of the total area. Furthermore, in order to reduce power consumption, circuit design techniques are also extensively applied to RAMs. ROMs, and clock circuits, which consume the great majority of power. By reducing the number of precharging bit lines, a power reduction of 49.8% is achieved in RAMs, and above 40% in ROMs. By applying gated clock to clock lines, a power reduction of 5.0% is achieved in the DSP that performs the PSI-CELP algorithm. The DSP is fabricated in 0.5 µm single-poly, double-metal CMOS technology. The PSI-CELP algorithm for the PDC half-rate CODEC can operate at 22.5 MHz instruction frequency and 1.6 V supply voltage. resulting in a low-power consumption of 28 mW.

Discussed here is reduction of power dissipation for multi-media LSIs. First, both active power dissipation Pat and stand-by power dissipation Pst for both CMOS LSIs and GaAs LSIs are summarized. Then, general technologies for reducing Pat are discussed. Also reviewed are a wide variety of approaches (i.e., parallel and pipeline schemes, Chen's fast DCT algorithms, hierarchical search scheme for motion vectors, etc.) for reduction of Pat. The last part of the paper focuses on reduction of Pst. Reducing both Pat and Pst requires that both throughput and active chip areas be either maintained or improved.

In this paper we propose a direct sequence spread spectrum (DS/SS) modulation method which employs Gaussian-filtered minimum shift keying (GMSK) and permits simple code acquisition. A transmitter which includes a conventional GMSK modulator and pseudo-noise (PN) code generator can achieve the proposed modulation method. The received signal can be demodulated by four-phase correlator which can obtain the correlation value of received signal even if phase difference exists between the transmitter and the receiver. The modulation method employs phase-shift-keying (PSK) by modulating the phase of transmitted PN code for data transmission. We carried out hardware experiments and the measured bit error performance ensures the validity of this modulation method. Then we designed and developed a demodulator LSI which is applicable to a modulation method such as the DS/GMSK/PSK. The LSI is suitable for demodulation of spreadspectrum signal which can be demodulated by four-phase correlator.

New interference cancellation technique using time division reference signal is proposed for optical synchronous code-division multiple-access (CDMA) systems with modified prime sequence codes. In the proposed system one user in each group is not allowed to access the network at each time, and this unallowable user's channel is used as a reference signal for other users in the same group at the time. The performance of the proposed system using an avalanche photodiode (APD) is analyzed where the Gaussian approximation of the APD output is employed and the effects of APD noise, thermal noise, and interference for the receiver are included. The proposed cancellation techniqus is shown to be effective to improve the bit error probability performance and to alleviate the error floor when the number of users and the received optical power are not appreciably small.

A V-band compact monolithic up-converter and down-converter were designed and tested. Each frequency converter was highly integrated with RF and LO amplifiers into a single compact chip. To avoid undesirable resonance, the chip width was limited to 0.9 mm. The up-converter has a balanced configuration to suppress undesired LO leakage. Using the uniplanar concept, the chip size of each frequency converter was greatly reduced to only 2.6 mm2. Measured performance of the up-converter includes conversion gain of-10.6 dB3.3 dB for a bandwidth of 10 GHz, and LO leakage is more than 10 dB below LO input. The down-converter shows a conversion gain of -0.4 dB2.0 dB.

In this paper, a design of a new processor array architecture with effective data storage schemes which meets the practical requirement of a reduced number of processor elements is proposed. Its design method is shown to be drastically simpler than the popular systolic arrays. This processor array which we call Memory Sharing Processor Array (MSPA) consists of a processor array, several memory units, and some address generation hardware units used to minimize the number of I/O ports. MSPA architecture with its design methodology tries to overcome overlapping data storages, idle processing time and I/O bottleneck problems, which mostly degrade the performance of systolic architecture. It has practical advantages over the systolic array in the view of area-efficiency, high throughput and practical input schemes.

This paper gives an overview of the research and development trends in millimeter-wave short-range application systems, such as communication systems and sensing systems, in Japan and other countries. Frequency management trends are also described. Major research and development efforts in Japan have currently been concentrated on the 59-64 GHz band. The first major achievement resulting from those efforts was the allocation of the 60-61 GHz band to the automotive radar systems. Test productions of automotive radars in this band have already started. Further technological developments to reduce the cost and size of radar products are, however, required in order for such radar systems to be widely used. Development of broadband wireless LAN systems has also been intensively made in the 60 GHz band. In addition, technical issues related to standardization of millimeter-wave wireless LAN systems in the 60 GHz band have been examined at the Association of Radio Industries and Businesses. The application areas of millimeter-waves in the future are expected to become more diverse. Research and development trends of future application systems, such as broadband mobile communication systems and imaging radar systems, are also described. These systems require more advanced millimeter-wave technologies, such as smart antennas, low power-consumption devices, and more sensitive detectors. Efforts to develop these technologies must be strengthened.

This paper deals with the synthesis of Petri nets. Partial languages adequately represent the concurrent behaviors of Petri nets. We first propose a construction problem for Petri nets, in which the objective is to synthesize a Petri net to exhibit the desired behavior specified as a partial language. We next discuss the solvability of this problem and last present the cutline of a solution technique.

In this paper, an exact-minimization method for an AND-EXOR expression (ESOP) using O-suppressed binary decision diagrams (ZBDDs) is considered. The proposed method is an improvement of Sasao's MRCF-based method. From experimental results, it is shown that required ZBDD size is reduced to 1/3 in the best case compared with the MRCF-based method.

In [2] Ibarra introduced a restricted version of one-way multihead pushdown automaton (PDA), called a simple one-way multihead PDA, and showed that such machines recognize only languages with semilinear property. The main result of this paper is that for each k 1, simple (sensing) one-way (k + 1)-head PDA's are more powerful than simple (sensing) one-way k-head PDA's. This paper also investigates closure properties for simple (sensing) one-way multihead PDA's

The polymer matrix for the number of N in-puts/outputs, N stages and 2x2-switches is denoted as the 1-D Spanke-Benes (SB) network. Throughout the paper, the 1-D SB-network, which equals the diamond cellular array, is extended to arbitrary dimensions by a mathematical transformation (a 1-D network provides the interconnection of 1-D data). This transformation determines the multistage architecture completely by providing size, location, geometry and wiring of the switches as well as it preserves properties of the networks, e.g., the capability of sorting. The SB-networks of dimension 3 are analysed and sorting is applied.

This paper evaluates the performance of DS/CDMA with diversity coding and multiuser interference (MUI) cancellation in fading multipath channel. The diversity technique considered in this paper, is different from the conventional scheme and transmits different information over different channels. It is shown that, this diversity scheme performs better than conventional diversity scheme, and when combined with MUI cancellation provides significant performance improvement. Effects of partial band jamming on the system are also considered.

We describe low supply voltage analog circuit techniques for voice- and audio-band interfaces. These techniques can lower the supply voltage to 1 V, which is the voltage of a one-NiCd-cell battery. We have applied them in a swingsuppression noise-shaping method, and using this method, have fabricated A/D and D/A converters for the voice and audio bands. These converters operate with a 1 V power supply and have 13-bit and 17-bit accuracy in the audio-band and power consumption of about 1 mW. This performance proves that our techniques are sufficient for baseband analog interfaces.

Recently , a short range millimeter wave or a microwave sensing system has been extensively studied to estimate a target position or a source location. It can be applied to indoor propagation analysis, carborne applications, etc. The application of the superresolution technique has been proposed to obtain a high resolution performance in the time domain or the spatial domain. However, the availability of the polarization synthesis in the receiving antennas has not been considered. In this paper, we use a pair of polarized swept frequency data and propose two modifications of the MUSIC algorithm to enhance the resolution of time delay. One modification is the correlation matrix formulation which relates to the total signal power, and the other is a polarization filtering applied to the correlation matrix. These modifications have advantages such that. 1)Reduction of the estimation problem to the delay time estimation only; 2)Easy implementation. Experimental results are illustrated to show the availability of the methods, and to confirm the high resolution performance compared with the conventional method.