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14461-14480hit(16314hit)

  • Device Technology for Monolithic Integration of InP-Based Resonant Tunneling Diodes and HEMTs

    Kevin Jing CHEN  Koichi MAEZAWA  Takao WAHO  Masafumi YAMAMOTO  

     
    PAPER

      Vol:
    E79-C No:11
      Page(s):
    1515-1524

    This paper presents the device technology for monolithic integration of InP-based resonant tunneling diodes (RTDs) and high electron mobility transistors (HEMTs). The potential of this technology for applications in quantum functional devices and circuits is demonstrated in two integration schemes in which RTDs and FETs are integrated either in Parallel or in series. Based on the parallel integration scheme, we demonstrate an integrated device which exhibits negative differential resistance and modulated peak current. This integrated device forms the foundation of a new category of functional circuits featuring clocked supply voltage. Based on the series integration scheme, resonant-tunneling high electron mobility transistors (RTHEMTs) with novel current-voltage characteristics and useful circuit applications are demonstrated. The high-frequency characteristics of RTHEMTs are also reported.

  • Effects of Simulated Annealing in the Resonant-Tunneling Resistive-Fuse Network for Early Vision

    Koichi MAEZAWA  

     
    PAPER

      Vol:
    E79-C No:11
      Page(s):
    1543-1549

    The resistive-fuse network for early vision was studied using circuit simulation to clarify the potential of implementation with resonant tunneling diodes (RTDs). To over-come the fundamental problem of the RTD network, i.e., the RTDs cannot perform simulated annealing (SA), pseudo SAs were proposed. These methods are based on the time-variation of the input signal strength, and are found to be effective in restoring images. A resistive-fuse network is shown to be one of the most promising applications of RTDs.

  • Negative-Resistance Analysis of Colpitts Crystal Oscillators with a Tank Circuit

    Masayuki HANAZAWA  Yasuaki WATANABE  Hitoshi SEKIMOTO  

     
    LETTER

      Vol:
    E79-A No:11
      Page(s):
    1841-1843

    This paper describes a circuit analysis technique that includes all circuit elements used in transistor Colpitts quartz crystal oscillators. This technique is applied to a quartz crystal oscillator that has a tank circuit for selecting the oscillation frequency. The results obtained with this technique are compared with SPICE simulation results. Good agreement in the results clearly shows the validity of our technique.

  • Codimension Two Bifurcation Observed in a Phase Converter Circuit

    Hiroyuki KITAJIMA  Tetsuya YOSHINAGA  Hiroshi KAWAKAMI  

     
    PAPER-Nonlinear Circuits and Bifurcation

      Vol:
    E79-A No:10
      Page(s):
    1563-1567

    We investigate bifurcations of the periodic solution observed in a phase converter circuit. The system equations can be considered as a nonlinear coupled system with Duffing's equation and an equation describing a parametric excitation circuit. In this system there are two types of solutions. One is with x = y = 0 which is the same as the solution of Duffing's equation (correspond to uncoupled case), another solution is with xy0. We obtain bifurcation sets of both solutions and discuss how does the coupling change the bifurcation structure. From numerical analysis we obtain a codimension two bifurcation which is intersection of double period-doubling bifurcations. Pericdic solutions generated by these bifurcations become chaotic states through a cascade of codimension three bifurcations which are intersections of D-type of branchings and period-doubling bifurcations.

  • SPICE Oriented Steady-State Analysis of Large Scale Circuits

    Takashi SUGIMOTO  Yoshifumi NISHIO  Akiko USHIDA  

     
    PAPER-Nonlinear Circuits and Bifurcation

      Vol:
    E79-A No:10
      Page(s):
    1530-1537

    In this paper, we propose a novel SPICE oriented steady-state analysis of nonlinear circuits based on the circuit partition technique. Namely, a given circuit is partitioned into the linear and nonlinear subnetworks by the application of the substitution theorem. Each subnetwork is solved using SPICE simulator by the different techniques of AC analysis and transient analysis, respectively, whose steady-state reponse is found by an iteration method. The novel points of our algorithm are as follows: Once the linear subnetworks are solved by AC analysis, each subnetwork is replaced by a simple equivalent RL or RC circuit at each frequency component. On the other hand, the reponse of nonlinear subnetworks are solved by transient analysis. If we assume that the sensitivity circuit is approximated at the DC operational point, the variational value will be also calculated from a simple RL ro RC circuit. Thus, our method is very simple and can be also applied to large scale circuits, effciently. To improve the convergency, we introduce a compensation technique which is usefully applied to stiff circuits containing components such as diodes and transistors.

  • Acceleration Techniques for Waveform Relaxation Approaches to Coupled Lossy Transmission Lines Circuit Analysis Using GMC and GLDW Techniques

    Takayuki WATANABE  Hideki ASAI  

     
    PAPER-Nonlinear Circuits and Bifurcation

      Vol:
    E79-A No:10
      Page(s):
    1538-1545

    This paper describes a waveform relaxationbased coupled lossy transmission line circuit simulator DESIRE3T+. First, the generalized method of characteristics (GMC) is reviewed, which replaces a lossy transmission line with an equivalent disjoint network. Next, the generalized line delay window (GLDW) partitioning technique is proposed, which accelerates the transient analysis of the circuits including transmission lines replaced by GMC model. Finally GMC model and GLDW technique are implemented in hte relaxation-based circuit simulator DESIRE3T+ which can analyze bipolar transistor circuits by using the dynamic decomposition technique, and the performance is estimated.

  • Satsuki: An Integrated Processor Synthesis and Compiler Generation System

    Barry SHACKLEFORD  Mitsuhiro YASUDA  Etsuko OKUSHI  Hisao KOIZUMI  Hiroyuki TOMIYAMA  Hiroto YASUURA  

     
    PAPER-Hardware-Software Codesign

      Vol:
    E79-D No:10
      Page(s):
    1373-1381

    Entire systems on a chip (SOCs) embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16-word register file.

  • Self-Synchronized Syntax for Error-Resilient Video Coding

    Yasuko MATSUMURA  Toshihisa NAKAI  

     
    PAPER

      Vol:
    E79-B No:10
      Page(s):
    1467-1473

    Moving-picture transmission through narrow band and high bit error rate communication channels, such as a mobile communication channel, requires improved compression rate and enhanced error resilience. Variable-length codes are one of the essential techniques of compressing digital video information. This technique is used in various video coding schemes although a bit error in the channel impairs the synchronization of variable-length codewords, resulting in propagation of the error. With a hybrid video coding method in particular, which combines motion-compensation and transform coding, once an error is detected in the coded data, subsequent data cannot be decoded. Consequently, even an error-free portion of any data received must be discarded. To minimize the influence of an error in a channel on coded video data, this paper proposes a new video coding syntax which makes the best use of the self synchronizing characteristic of variable-length Huffman codes. Owing to the Huffman code's characteristic, the proposed coding syntax enables a decoder to decode the data portion that cannot be decoded, due to an error, by the conventional syntax without adding any redundancy. Computer simulation has verified the effectiveness of this proposed syntax in video coding with a very low bitrate and erroneous communication channel.

  • Performance Analysis of Modified/Quadrature Partial Response-Trellis Coded Modulation (M/QPR-TCM) Systems

    Osman Nuri UCAN  

     
    PAPER-Mobile Communication

      Vol:
    E79-B No:10
      Page(s):
    1570-1576

    In this paper partial response signalling and trellis coded modulation are considered together to improve bandwidth efficiency and error performance for M-QAM and denoted as Modified/Quadrature Partial Response-Trellis Coded Modulation (M/QPR-TCM) and two new non-catastrophic schemes M/6QPR-TCM and M/9QPR-TCM are introduced for 4QAM. In colored noise with correlation coefficient less than zero, the proposed schemes perform better than in AWGN case. Another interesting result is that when the combined system is used on a Rician fading channel, the bit error probability upper bounds of the proposed systems are better than their counterparts the 4QAM-TCM systems with 2 and 4 states, respectively, for SNR values greater than a threshold, which have the best error performance in the literature.

  • Coupling Efficiency of Grating Coupler for the Gaussian Light Beam Incidence

    Masaji TOMITA  

     
    PAPER

      Vol:
    E79-C No:10
      Page(s):
    1420-1429

    In this paper, scattering problem of the grating coupler is analyzed by the mode-matching method in the sense of least squares for the gaussian light beam incidence. This coupler has a periodic groove structure of finite extent, which is formed on the surface of the core layer of the symmetric thin-film waveguide. In the present method, the approximate scattered fields of each region of the grating coupler are described by the superpositions of the plane waves with band-limited spectra, respectively. These approximate wave functions are determined by the minimization of the mean-square boundary residual. This method results in the simultaneous Fredholm type integral equations of the second kind for these spectra. The first and second order approximate solutions of the integral equations are derived analytically and the coupling efficiency and scattered fields are analyzed on the basis of those solutions. A qualitative and physical consideration for the scattering problem of the grating coupler is presented with the fundamental data derived from approximate solutions in this paper.

  • Some Characteristics of Higher Order Neural Networks with Decreasing Energy Functions

    Hiromi MIYAJIMA  Shuji YATSUKI  Michiharu MAEDA  

     
    PAPER-Neural Nets and Human Being

      Vol:
    E79-A No:10
      Page(s):
    1624-1629

    This paper describes some dynamical properties of higher order neural networks with decreasing energy functions. First, we will show that for any symmetric higher order neural network which permits only one element to transit at each step, there are only periodic sequences with the length 1. Further, it will be shown that for any higher order neural network, with decreasing energy functions, which permits all elements to transit at each step, there does not exist any periodic sequence with the length being over k + 1, where k is the order of the network. Lastly, we will give a characterization for higher order neural networks, with the order 2 and a decreasing energy function each, which permit plural elements to transit at each step and have periodic sequences only with the lengh 1.

  • A Novel Technique of Harmonic Rejection of the Sequential Type PLL Phase Detector and Its Application to Single-Loop Frequency Synthesis

    S. K. SEN  S. SARKAR  P. K. GUPTA  

     
    LETTER-Microwave and Millimeter Wave Technology

      Vol:
    E79-C No:10
      Page(s):
    1467-1471

    This letter demonstrates that, under certain condition, the harmonic content of a rectangular pulse train is reduced by a considerable extent in the presence of another equal frequency pulse train of opposite polarity. The condition for maximum harmonic rejection is derived. It is also shown that this technique can, very effectively, be applied to reduce the harmonic content of a sequential phase detector (PD) output. This letter also presents the experimental performance of a sequential PD, incorporating this technique, in a single-loop synthesizer.

  • A Contraction Algorithm Using a Sign Test for Finding All Solutions of Piecewise-Linear Resistive Circuits

    Kiyotaka YAMAMURA  Masakazu MISHINA  

     
    LETTER-Nonlinear Problems

      Vol:
    E79-A No:10
      Page(s):
    1733-1736

    An efficient algorithm is proposed for finding all solutions of piecewise-linear resistive circuits The algorithm is based on the idea of "contraction" of the solution domain using a sign test. The proposed algorithm is efficient because many large super-regions containing no solution are eliminated in early steps.

  • A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs

    Vasily G. MOSHNYAGA  Keikichi TAMARU  

     
    PAPER-High-Level Synthesis

      Vol:
    E79-D No:10
      Page(s):
    1389-1395

    As IC fabrication technology enters a deepsubmicron region with device feature sizes <0.35µm, interconnect becomes the most dominant factor in design of high-speed Application Specific Integrated Circuits (ASICs). This paper proposes a novel methodology for automated data-path synthesis of such circuits and outlines algorithms to support it. In contrast to other approaches, we formulate interconnect area/delay optimizations as high-level synthesis transformations and use them during the synthesis to minimize the impact of wiring on circuit characteristics. Experiments with FIR filter implementations show that such formulation jointly with on the fly" module generation and performance-driven floorplanning provides more than a 30% reduction in wiring delay for deep sub-micron designs.

  • Physical Optics Analysis of Dipole-Wave Scattering from a Finite Strip Array on a Grounded Dielectric Slab

    Shuguang CHEN  Yoshio SATO  Masayuki OODO  Makoto ANDO  

     
    PAPER

      Vol:
    E79-C No:10
      Page(s):
    1350-1357

    This paper verifies the accuracy of PO as applied to the scattering of dipole waves by a finite size reflector which is composed of strips on a grounded dielectric slab. By using the closed form expressions of reflected waves from the surface, PO calculation can be conducted straightforwardly. The calculated results are compared with the experimental ones for vertical and horizontal dipoles over a circular reflector.

  • Representation of Dynamic 3D Objects Using the Coaxial Camera System

    Takayuki YASUNO  Jun'ichi ICHIMURA  Yasuhiko YASUDA  

     
    PAPER

      Vol:
    E79-B No:10
      Page(s):
    1484-1490

    3D model-based coding methods that need 3D reconstruction techniques are proposed for next-generation image coding methods. A method is presented that reconstructs 3D shapes of dynamic objects from image sequences captured using two cameras, thus avoiding the stereo correspondence problem. A coaxial camera system consisting of one moving and one static camera was developed. The optical axes of both cameras are precisely adjusted and have the same orientation using an optical system with true and half mirrors. The moving camera is moved along a straight horizontal line. This method can reconstruct 3D shapes of static objects as well as dynamic objects using motion vectors calculated from the moving camera images and revised using the static camera image. The method was tested successfully on real images by reconstructing a moving human shape.

  • A Theorem on an Ω-Matrix Which is a Generalization of the P-Matrix

    Tetsuo NISHI  

     
    PAPER-Nonlinear Circuits and Bifurcation

      Vol:
    E79-A No:10
      Page(s):
    1522-1529

    The author once defined the Ω-matrix and showed that it played an important role for estimating the number of solutions of a resistive circuit containing active elements such as CCCS's. The Ω-matlix is a generalization of the wellknown P-matrix. This paper gives the necessary and sufficient conditions for the Ω-matrix.

  • Van der Pol Oscillators Coupled by Piecewise-Linear Negative Resistor Asynchronous Oscillations by Self-Modulation Effect

    Hiroyuki KANASUGI  Seiichiro MORO  Shinsaku MORI  

     
    PAPER-Nonlinear Circuits and Bifurcation

      Vol:
    E79-A No:10
      Page(s):
    1551-1562

    In this study, we investigate two oscillators which have the same natural frequency, mutually coupled by N-type piecewise-linear negative resistor. In this system, according to the negative range of the coupling negative resistor, the various inter-esting synchronization phenomena which are in-phase, opposite phase and doublemode-like oscillations are observed. Especially, we show doublemode-like oscillations that are not observed until now in mutually coupled van der Pol oscillators with the smooth cubic characteristics, although the ones with same natural frequencies are coupled. And we show the differences of the phenomena between two oscillators coupled by the smooth cubic negative resistor and the ones coupled by the piecewise-linear negative resistor.

  • ASYL-SdF: A Synthesis Tool for Dependability in Controllers

    Raphael ROCHET  Regis LEVEUGLE  Gabriele SAUCIER  

     
    PAPER-High-Level Synthesis

      Vol:
    E79-D No:10
      Page(s):
    1382-1388

    Synthesis tools are now extensively used in the VLSI circuit design process. They allow a much higher design productivity, but the designer often does not directly control the circuit structure. Thus, when circuits are dedicated to dependable applications, designers have difficulties in implementing manually the devices needed to obtain fault detection or tolerance capabilities. The ASYL-SdF System has been developed over the last few years in order to avoid this break in the design flow, and to facilitate the designer's work when dependability is targeted. This paper gives an overview of the resulting tool, its synthesis flow for fault detection and fault tolerance in Finite State Machines, its limitations and the current developments. Actual circuit implementation results are given in terms of area overheads, expected reliability and experimental fault detection coverage.

  • General Frame Multiresolution Analysis and Its Wavelet Frame Representation

    Mang Ll  Hidemitsu OGAWA  Yukihiko YAMASHITA  

     
    PAPER-Digital Signal Processing

      Vol:
    E79-A No:10
      Page(s):
    1713-1721

    We propose a theory of general frame multiresolution analysis (GFMRA) which generalizes both the theory of multiresolution analysis based on an affine orthonormal basis and the theory of frame multiresolution analysis based on an affine frame to a general frame. We also discuss the problem of perfectly representing a function by using a wavelet frame which is not limited to being of affine type. We call it a "generalized affine wavelet frame." We then characterize the GFMRA and provide the necessary and sufficient conditions for the existence of a generalized affine wavelet frame.

14461-14480hit(16314hit)