This paper describes numerical analyses of resistive mixer operation, followed by measured performances of a V-band (50 - 75 GHz) monolithic InP HEMT resistive mixer operable with a very low LO power. Our model assumes that the channel conductance of the InP HEMT can be described by three linear functions according to the applied gate voltage. The calculated results obtained with the model have shown that the LO power level required for mixer operation is determined by the gate bias voltage and that a device with abrupt conductance shifts is suited to low LO power operation for a resistive mixer. It is also shown that conversion loss saturation of a resistive mixer is caused by its channel conductance saturation. A V-band monolithic resistive mixer has been designed and fabricated using Coplanar Waveguides (CPW) and a 0.15 mm InP HEMT with abrupt channel shifts. Good agreement between measured and simulated conversion losses are obtained. A minimum conversion loss of 8.4 dB is achieved at the 55 GHz RF-frequency and the -2 dBm LO power. It also exhibits an excellent IF output linearity to allow the 1 dB compression RF input level to be comparable with LO power, indicating good intermodulation performance. It is demonstrated that the proposed simple model of the channel conductance can easily calculate conversion characteristics of a resistive mixer with high accuracy.

This paper presents an improved method of speaker verification using the sequential probability ratio test (SPRT), which can treat the correlation between successive feature vectors. The hidden Markov model with the mean field approximation enables us to consider the correlation in the SPRT, i. e. , using the mean field of previous state, probability computation can be carried out as if input samples were independent each other.

For the realization of low-voltage full-color FEDs, requirements for phosphor for the FED are proposed. Especially, the influence of released gases or substances from phosphors on the field emission within the FED was made clear. It was clarified that the analysis of F-N plots of the V-I curve of field emission characteristics was helpful to know the interaction of field emission and phosphors. In the experiment, we first obtained the depth from the phosphor surface of the low voltage electron excitation in case of ZnGa2O4, where the region available for cathodoluminescence at the anode voltage of 400 V is about 63 nm deep from the surface. The characteristic of the 12.4 cm-320(trio)240 pixels low-voltage full-color FED is reported. The luminance of 154 cd/m2 was attained at the anode voltage of 400 V and the duty factor of 1/241. Supported by the high potential of the FED as a flat panel, each problem shall be steadily solved to secure the firm stand as a new full color flat display in new applications.

In this paper, we consider sufficient conditions for ruling out some useless iteration steps in a class of soft-decision iterative decoding algorithms for binary block codes used over the AWGN channel using BPSK signaling. Sufficient conditions for ruling out the next single decoding step, called ruling-out conditions and those for ruling out all the subsequent iteration steps, called early termination conditions, are formulated in a unified way without degradation of error performance. These conditions are shown to be a type of integer programming problems. Several techniques for reducing such an integer programming problem to a set of subprograms with smaller computational complexities are presented. As an example, an early termination condition for Chase-type decoding algorithm is presented. Simulation results for the (64, 42, 8) Reed-Muller code and (64, 45, 8) extended BCH code show that the early termination condition combined with a ruling-out condition proposed previously is considerably effective in reducing the number of test error patterns, especially as the total number of test error patterns concerned grows.

Since cryptosystem based on the problem of factoring the composite number N can be attacked with P-1 and P+1 methods, it is required that P-1 and P+1 should be difficult to be factored into many small primes, where we assume that the P is a factor of N. In this paper, first, we consider the distribution of secure primes against both P-1 and P+1 methods. Second, we propose two efficient algorithms for generating secure primes against both P-1 and P+1 methods by extending the trial division method.

One of the limitation factors on the achievable distance for long-haul nonlinear Return-to-Zero (RZ)-Gaussian pulse transmission on optical fiber links is timing jitter. Although it is well known that the dispersion management technique is very effective to reduce the timing jitter, comparisons among some dispersion management methods based on the timing jitter reduction have not been reported yet. In this paper, timing jitter reduction by some dispersion management methods in nonlinear RZ-Gaussian pulse transmission systems are discussed. Moreover, we will report that the amount of timing jitter at the receiver side drastically changes depending on the configuration of dispersion managed optical fiber transmission line.

Simple computation method of soft value, that is used in iterative soft decision decoding, is proposed. For the product code composed of BCH(63, 57) and that composed of BCH(63, 45), computation time with the proposed method is 1/15-1/6 as that with a method based on the Chase algorithm. Bit error rate (BER) performance with the proposed method is within 0.8 [dB] inferior to that with the method based on the Chase algorithm at BER=10-5.

The minimum mean-squared error (MMSE) linear detector has been proposed to successfully suppress the multiple access interference and mitigate the near-far problem in direct-sequence code-division multiple access communication systems. In the presence of unknown or time-varying channel parameters, the MMSE linear detector can be implemented by the blind Griffiths' algorithm, which uses the desired signal vector instead of a training sequence of symbols for initial adaptation. In this paper, a variable step-size (VSS) Griffiths' algorithm is proposed for accelerating the convergence speed, especially in the presence of strong interference. Numerical results show that the convergence properties of the VSS Griffiths' algorithm are robust against the wide eigenvalue-spread problem of the correlation matrix associated with the received signal vector compared to the Griffiths' algorithm using a fixed step-size.

In this paper, soft decision decoding of linear block codes based on the reprocessing of several information sets is considered. These information sets are chosen according to the reliability measures of the received symbols and constructed from the most reliable information set, referred to as the most reliable basis. Each information set is then reprocessed by a multi-stage decoding algorithm until either the optimum error performance, or a desired level of error performance is achieved. General guidelines for the trade-offs between the number of information sets to be processed, the number of computations for reprocessing each information set, and the error performance to be achieved are provided. It is shown that with a proper selection of few information sets, low-complexity near-optimum soft decision decoding of relatively long block codes (64 N 128) can be achieved with significant reduction in computation complexity with respect to other known algorithms. This scheme, which generalizes the reprocessing of the most reliable basis with the ordered statistic algorithm proposed by Fossorier and Lin, is particularly efficient for codes with rate R 1/2.

This paper clarifies two variable-to-fixed length codes which achieve optimum large deviations performance of empirical compression ratio. One is Lempel-Ziv code with fixed number of phrases, and the other is an arithmetic code with fixed codeword length. It is shown that Lempel-Ziv code is asymptotically optimum in the above sense, for the class of finite-alphabet and finite-state sources, and that the arithmetic code is asymptotically optimum for the class of finite-alphabet unifilar sources.

Human visual system can perceive 3-D structure of an object by binocular disparity, gradient of illumination (shading), occlusion, textures, perspective and so forth. Among them, binocular disparity seems to be the essentially important cues for the 3-D space perception and it is used widely for displaying 3-D visual circumstances such as in VR (virtual reality) system or 3-D TV. Visual illusions seem to be one of the phenomena which are purely reflecting the mechanism of human visual system. In the recent several years, the authors found several new types of 3-D visual illusions with binocular viewing. Entire 3-D illusory object including volume perception, transparency, dynamic illusions can be perceived only from the visual stimuli of disparity given by some inducing objects arranged with suitable relations. In this report, the authors introduced these newly found visual illusions and made some considerations on the human visual mechanism of 3-D perception and on their exploitation for new effective techniques in 3-D display. They introduced especially on the visual effect in two kinds of arrangement with occlusion and sustaining relationship between the illusory object and inducing objects. In the former case, the inducing objects which provide the stimuli were named as occlusion cues and classified into two types: contour occlusion cues and bulky occlusion cues. In the later case, those inducing objects were named as sustaining cues and a 3-D fully transparent illusory object was perceived. The perception was just like imagined from the scenes of the actions and positions of the pantomimists; then this phenomena was named as "Mime (Pantomime) Effect. " According to the positions of sustaining cues, they played different actions in this perception, and they are classified into three types: front sustaining cues, side sustaining cues and back sustaining cues. In addition, dynamic fusion and separation of volumetrical illusory objects were perceived when the visual stimuli were moving continuously between two structurally different conditions. Then the hysteresis was recognized in geometrical position between the fusion and separation. The authors believe that the occlusion cues and sustaining cues introduced in this paper could be effective clues for exploiting the new techniques for 3-D display.

This paper presents a performance evaluation of NAK-based reliable multicast communication protocols operating in an environment where end-to-end delay are heterogeneous. In the case of heterogeneous delay, performance of a timer-based retransmission control scheme may become worse. We show that a counter-based retransmission control scheme works well in the case of heterogeneous transmission delay. We also compare two NAK-based protocols and show that a NAK-multicasting protocol outperforms a NAK-unicasting protocol from the viewpoint of scalability even when delays are heterogeneous.

In this paper, we focus on regularity and set-valued functions. Regularity was first introduced by S. C. Kleene in the propositional operations of his ternary logic. Then, M. Mukaidono investigated some properties of ternary functions, which can be represented by regular operations. He called such ternary functions "regular ternary logic functions". Regular ternary logic functions are useful for representing and analyzing ambiguities such as transient states or initial states in binary logic circuits that Boolean functions cannot cope with. Furthermore, they are also applied to studies of fail-safe systems for binary logic circuits. In this paper, we will discuss an extension of regular ternary logic functions into r-valued set-valued functions, which are defined as mappings on a set of nonempty subsets of the r-valued set {0, 1, . . . , r-1}. First, the paper will show a method by which operations on the r-valued set {0, 1, . . . , r-1} can be expanded into operations on the set of nonempty subsets of {0, 1, . . . , r-1}. These operations will be called regular since this method is identical with the way that Kleene expanded operations of binary logic into his ternary logic. Finally, explicit expressions of set-valued functions monotonic in subset will be presented.

We proposed a soft-decision decoding algorithm for cyclic codes based on energy minimization principle. This letter presents the algorithm which improves decoding performance and decoding complexity of the previous method by giving more initial positions and introducing a new criterion for terminating the decoding procedure. Computer simulation results show that both the decoded block error rate and the decoding complexity decrease by this method more than by the previous method.

In order to lead an ongoing software project to success, it is important to flexibly control its dynamically-changing software process. However, it is generally impossible not only to exactly pre-define the production process but also to prescribe the process change process (meta-process). To solve the problem, we have focused on communication between the project staff through which process change requests presented by individuals can be immediately shared, designed, verified, validated and implemented. This paper proposes a communication model which can represent a wide variety of communication states between the project manager and developers discussing how to implement process change requests. The communication model has been derived by investigating the sort of process change requests and, based on the model, we have implemented a cooperative process planning system (called CooPs). CooPs is a communication environment designed for software projects and supports information sharing for discussing the process change requests. By using CooPs, the software project can flexibly deal with not only expected change requests but also unexpected ones. To evaluate the applicability of the communication model and the capabilities of CooPs, we have conducted an experiment which is an application of CooPs to the ISPW6 example problem. This paper describes the concepts of CooPs, the system implementation, and the experiment.

Using Hopfield-type neural network model, we present an algorithm for reconstructing 3D mesh processor arrays using single-track switches where spare processors are laid on the six surfaces of a 3D array and show its effectiveness in terms of reconstruction rate and computing time by computer simulation. Next, we show how the algorithm can be realized by a digital neural circuit. It consists of subcircuits for finding candidate compensation paths, deciding whether the neural system reaches a stable state and at the time the system energy is minimum, and subcircuits for neurons. The subcircuit for each neuron including the other subcircuits can only be made with 16 gates and two flip-flops. Since the state transitions are done in parallel, the circuit will be able to find a set of compensation paths for a fault pattern very quickly within a time less than 1 µs. Furthermore, the hardware implementation of the algorithm leads to making a self-reconfigurable system without the aid of a host computer.

An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-µm double-polysilicon CMOS technology with the chip size of 7.2 mm 7.2 mm, and the basic operation of the circuits has been demonstrated.

High-speed collision detection is important to realize a highly-safe intelligent vehicle. In collision detection, high-computational power is required to perform matching operation between discrete points on surfaces of a vehicle and obstacles in real-world environment. To achieve the highest performance, a hierarchical matching scheme is proposed based on two representations: the coarse representation and the fine representation. A vehicle is represented as a set of rectangular solids in the fine representation (fine rectangular solids), and the coarse representation, which is also a set of rectangular solids, is produced by enlarging the fine representation. If collision occurs between an obstacle discrete point and a rectangular solid in the coarse representation (coarse rectangular solid), then it is sufficient to check the only fine rectangular solids contained in the coarse one. Consequently, checks for the other fine rectangular solids can be omitted. To perform the hierarchical matching operation in parallel, a hierarchically-content-addressable memory (HCAM) is proposed. Since there is no need to perform matching operation in parallel with fine rectangular solids contained in different coarse ones, the fine ones are mapped onto a matching unit. As a result, the number of matching units can be reduced without decreasing the performance. Under the condition of the same execution time, the area of the HCAM is reduced to 46.4% in comparison with that of the conventional CAM in which the hierarchical matching scheme is not used.

This paper proposes applications of a code-division multiplexing technique to VLSI systems free from interconnection problems. We employ a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier to achieve efficient data transmission. Using orthogonal property of m-sequences, we can multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission with reduced interconnection. Also, randomness of m-sequences offers the high tolerance to interference (jamming), and suppression of dynamic range of signals while maintaining a sufficient signal-to-noise ratio (SNR). We demonstrate application examples of multiplex computing circuits, neural networks, and spread-spectrum image processing to show the advantages.

This paper gives a detailed presentation of a "vision chip" for a very fast detection of motion vectors. The chip's design consists of a parallel pixel array and column parallel block-matching processors. Each pixel of the pixel array contains a photo detector, an edge detector and 4 bits of memory. In the detection of motion vectors, first, the gray level image is binarized by the edge detector and subsequently the binary edge data is used in the block matching processor. The block-matching takes place locally in pixel and globally in column. The chip can create a dense field of motion where a vector is assigned to each pixel by overlapping 2 2 target blocks. A prototype with 16 16 pixels and four block-matching processors has been designed and implemented. Preliminary results obtained by the prototype are shown.