This paper presents a new analysis result of two-dimensional four-phase abdominal CT images using variational Bayesian mixture of ICA. The four-phase CT images are assumed to be comprised of several exclusive areas, and each area is generated by a set of corresponding independent components. ICA mixture analysis results show that the CT images could be divided into a set of clinically and anatomically meaningful components. Initial analysis of the independent components shows its promising prospects in medical image processing and computer-aided diagnosis.

This paper introduces a methodology for simulating single-electron-transistor (SET)-based multiple-valued logics (MVLs). First, a physics-based analytical model for SET is described, and then a procedure for extracting parameters from measured characteristics is explained. After that, simulated and experimental results for basic MVL circuits are compared. As an advanced example of SET-based logics, a latched parallel counter, which is one of the most important components in arithmetic circuits, is newly designed and analyzed by a simulation. It is found that a SET-based 7-3 counter can be constructed with less than 1/10 the number of devices needed for a conventional circuit and can operate at a moderate speed with 1/100 the conventional power consumption.

The carbon nanotube field-effect transistors show the hysteresis characteristic in their electrical characteristics owing to the amorphous carbon around the carbon nanotube. It is shown here the reduction of the hysteresis characteristic by the refining process applied repeatedly to the carbon nanotube. Moreover, after the refining processes, the transconductance of carbon nanotube field-effect transistor becomes 2.0 µS the ten times larger than before the refining process. Almost all carbon nanotubes without the refining processes, grown by thermal chemical vapor deposition, show the p type semiconductor characteristics. After the refining processes on the other hand, almost all carbon nanotube show the ambipolar type semiconductor characteristics.

A new approach for ultra-low-power LSIs based on quantum devices is presented and its present status and critical issues are discussed with a brief background review on the semiconductor nanotechnology. It is a hexagonal binary decision diagram (BDD) quantum logic circuit approach suitable for realization of ultra-low-power logic/memory circuits to be used in new applications such as intelligent quantum (IQ) chips embedded in the ubiquitous network environment. The basic concept of the approach, circuit examples showing its feasibility, growth of high density nanostructure networks by molecular beam epitaxy (MBE) for future LSI implementation, and the key processing issues including the device isolation issue are addressed.

This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.

We propose an ultra low power watch-dog circuit with the use of MOSFETs operation under subthreshold characteristics. The circuit monitors the amount of the product degradation because the subthreshold current of MOSFET emulates the rate of the general chemical reaction. Its operation was verified with both SPICE simulation and the measurement of the prototype chip. The new circuit embedded in a tag attached to any product could dynamically monitor the degradation regardless of storage conditions.

This paper presents a multi-resolution optical flow estimation method that is robust against large variation in the estimation parameter. For each level solution of the multi-grid estimation, a nonlinear iteration is proposed differently from the existing method, where the incremental displacement from the coarser level optical flow is calculated by linear iteration. The experimental results show that the proposed scheme has better error-performance in a much wider range of regularization parameters.

Feedforward neural networks have been successfully developed and applied in many areas because of their universal approximation capability. However, there still remains the problem of determining a suitable network structure for the given task. In this paper, we propose a novel self-organizing neural network which automatically adjusts its structure according to the task. Utilizing both the constructive and the pruning procedures, the proposed algorithm finds a near-optimal network which is compact and shows good generalization performance. One of its important features is reliability, which means the randomness of neural networks is effectively reduced. The resultant networks can have suitable numbers of hidden neurons and hidden layers according to the complexity of the given task. The simulation results for the well-known function regression problems show that our method successfully organizes near-optimal networks.

Nonminimum phase systems are difficult to be controlled with a conventional PID-type controller because of their inherent characteristics of undershooting. A neuro-controller combined with a PID-type controller has been shown to improve the control performance of the nonminimum phase systems while maintaining stability. In this paper, we apply a multiobjective evolutionary optimization method for training the neuro-controller to reduce the undershooting of the nonminimum phase system. The computer simulation shows that the proposed multiobjective approach is very effective and suitable because it can minimize the control error as well as reduce undershooting and chattering. This method can be applied to many industrial nonminimum phase problems with ease.

In this paper, we consider the problem of multicast routing and wavelength assignment (MC-RWA) in multi-fiber all-optical WDM networks. Two main network design system comprehensively investigated here are mesh and multi-ring designs. Given the multicast traffic demands, we present new ILP formulations to solve the MC-RWA problem with an objective to determine the minimal number of fibers needed to support the multicast requests. Unlike previous studies, our ILP formulations are not only capable of finding the optimal multicast routing and wavelength assignment pattern to the light-trees, but also finding the optimal light-tree structures simultaneously. Since broadcast and unicast communications are special cases of multicast communications, our ILP models are actually the generalized RWA mathematical models of optical WDM networks. In addition to proposing the ILP models, this paper takes two main issues affecting the network capacity requirement into account, that is, the splitting degree level of optical splitters and techniques of wavelength assignment to the light-trees. Three multicast wavelength assignment techniques studied in this paper are Light-Tree (LT), Virtual Light-Tree (VLT) and Partial Virtual Light-Tree (PVLT) techniques. Due to the NP-completeness of the MC-RWA problem, the ILP formulations can reasonably cope with small and moderate networks. To work with large networks, this paper presents alternative MC-RWA ILP-based heuristic algorithms for the PVLT and LT networks and develops lower bound techniques to characterize the performance of our algorithms. Using existing large backbone networks, numerical results are reported to analyze such aspects as multiple fiber systems, the benefits of using optical splitters and wavelength converters, and the capacity difference between the mesh and multi-ring designs. Finally, this paper provides an analysis of the influence of network connectivity on the network implementation under the constraints of mesh and multi-ring design schemes.

Recently, a new light-weight version of the secure electronic transaction protocol was proposed. The protocol can achieve two goals. One goal is that the security level is the same as the SET protocol. The other goal is to reduce the computational time in message generation and verification, and reduce the communication overhead. However, the protocol has a weakness, which is that non-repudiation is acquired, but confidentiality is lost. In this paper, we point out the weakness of the protocol. We also propose an improvement to the protocol to overcome this weakness.

A novel Multiple-Valued Field-Programmable VLSI (MV-FPVLSI) architecture using the Multiple-Valued Source-Coupled Logic (MVSCL) is proposed to implement special-purpose processors. An MV-FPVLSI consists of identical cells, which are connected to 8-neighborhood ones. To reduce the complexity of the interconnection block between two cells in an MV-FPVLSI, a bit-serial fine-grain pipeline architecture is introduced which allows single-wire data transmission and as a result, the data-transmission delay becomes very small in comparison with that of a conventional FPGA. To reduce the number of switches in the interconnection block further, a cell, using multiple-valued source-coupled logic circuits, is proposed, where the input currents can be linearly summed just by wiring without using any active devices. Not only the data, but also the control signal can be superposed by linear summation. As a result, no input switch is required which contributes to smaller data transmission delay. Moreover, an arbitrary 2-input logic function can be generated by linear summation of the input currents and threshold operations using these reconfigurable MVSCL circuits. As the MVSCL circuit has high driving capability in comparison with that of an equivalent CMOS circuit, high-speed logic operation is also possible while maintaining low power.

To fulfill the computing demands in visual media processing, we have been investigating a parallel processing system to improve the processing speed of the visual media related to applications from the point of view of a memory system within a single instruction multiple data (SIMD) computer. In this paper, we have introduced MAMS-PP4, which is similar to a pipelined SIMD architecture type and consists of pq processing elements (PEs) as well as a multi-access memory system (MAMS). MAMS supports simultaneous access to pq data elements within a horizontal (1 pq), a vertical (pq 1) or a block (p q) subarray with a constant interval in an arbitrary position in an M N array of data elements, where the number of memory modules, m, is a prime number greater than pq. MAMS reduces the memory access time for an SIMD computer and also improves the cost and complexity that involved in controlling the large volume of data demanded in visual media applications. PE is designed to be a two-state machine in order to utilize MAMS efficiently. MAMS-PP4 was fabricated into ASIC using TOSHIBA TC240C series library and a test board was used to measure the performance of ASIC. The test board consists of devices such as an MPC860 embedded-PCI board, two ASICs and a FPGA for the control units. Experiment was done on various computer systems in order to compare the performance of MAMS-PP4 using morphological operations as the application. MAMS-PP4 shows a respectful and consistent processing speed.

We study analysis of hybrid systems under incomplete knowledge. The class of hybrid systems to be considered is assumed to have the form of a rectangular hybrid automaton such that each constant in invariants and guards is given as a parameter. We develop a method based on symbolic computation that computes an approximation of the discrete behavior of the automaton. We also show an implementation on a constraint logic programming language.

We develop an algorithm for a controller design method for Max-Plus Linear (MPL) systems with selective parameters. Since the conventional algorithm we proposed requires high computational load when the prediction horizon is large, two methods for reducing the calculation time are proposed. One is based upon the branch-and-bound method, and the other is to reuse the optimal solution. The effectiveness of these two methods is confirmed through numerical simulation.

A double surface light emission backlight that uses single light-guide plate, has been developed for illumination of two liquid-crystal displays (LCD) on its front and rear, to be used in a cellular phone. The light-guide plate has a trapezoid cross-section with arrays of optical micro deflector and micro prism on the front and the rear surfaces, respectively. Propagated light, forward and backward, inside the light-guide plate are controlled and directed toward LCDs using only two prism sheets with internal reflection characteristic, each for the front and the rear. Only three optical components and four light-emitting diodes (LEDs) are used in the new structure compared with ten components and six LEDs of the current type. Comparing with the current type, the thickness and power consumption of the new backlight are reduced by a factor of 0.59 and 0.67, respectively.

In this paper, we present a new numerical method for the complex approximation of FIR digital filters. Our objective is to design FIR filters with equiripple magnitude and phase errors. The proposed method solves the least squares (LS) problem iteratively. At each iteration, the desired response is updated so as to have an equiripple error. The proposed methods do not require any time-consuming optimization procedure such as the quasi-Newton methods and converge to equiripple solutions quickly. We show some examples to illustrate the advantages of our proposed methods.

We propose a multiple-subcarrier (MS) optical communication system using intensity modulation with direct detection (IM/DD) with peak reduction carriers (PRCs) to improve the power efficiency of IM/DD MS systems. The proposed system transmits L subcarriers referred to as PRCs among N subcarriers for the d.c. bias reduction so that the optical power is reduced. Since information bits are mapped onto each subcarrier other than PRCs independently, the information bits of each subcarrier can be detected independently and the error rate of the proposed system is unaffected by PRCs.

In this paper, we propose an optimal bit rate control algorithm which is fully compatible with MPEG-4 or H.263+. The proposed algorithm is designed to identify the optimal quantizer set through Lagrangian optimization when used for optimal bit allocation. To find the optimal quantizer set, we make use of the Viterbi algorithm in order to solve the dependency between quantization parameters of each macroblock due to the unique characteristics of MPEG-4 or H.263+. We set the Lagrangian cost function as a cost function of the Viterbi algorithm. We implement the proposed algorithm in MPEG-4 coders and compare its performance to the VM8 and optimal bit rate control algorithm, using independent quantization parameters in the circumstance of a low bit rate.

In this paper, a sub-optimal Rake receiver combined with a Wiener Filter is investigated for use in an indoor environment. Inner-Chip-interference is dominant when the application is indoors, so the inner-chip-interference rejection function becomes critical for the receiver. Pilot symbols in each slot are used for channel estimation and weight calculation of Rake combining through Wiener Filter. Compared to conventional combining which uses maximum ratio combining, Wiener combining using IRC (Interference rejection combining) achieves better ICI (Inner-chip-Interference) rejection. This paper clarified that the sub optimal Rake receiver using Wiener Filter is 4 dB better than the conventional Rake receiver under the indoor application.