In this paper, we present a new numerical method for the complex approximation of FIR digital filters. Our objective is to design FIR filters with equiripple magnitude and phase errors. The proposed method solves the least squares (LS) problem iteratively. At each iteration, the desired response is updated so as to have an equiripple error. The proposed methods do not require any time-consuming optimization procedure such as the quasi-Newton methods and converge to equiripple solutions quickly. We show some examples to illustrate the advantages of our proposed methods.

The optimum tier architectures for ASICs are investigated by using a methodology for predicting packing efficiency of a logic block (the ratio of total cell area to the block area including space regions between cells). In the methodology based on Rent's rule, (1) the empirical parameters required for the prediction are derived from the results of our ASIC products. (2) The concept of logic distance, which is expressed in units of the number of cells rather than the absolute net length, is introduced. (3) Not only performance constraints but also reliability constraints are incorporated. These allow us to make a quantitative comparison of the packing efficiency between various cell and tier structures. It is found that, for mega-cell blocks, all minimum-pitch layer architecture with buffer insertion is expected to give more than 20% reduction in block areas compared to the minimum-pitch + bi-pitch architecture, while satisfying the performance and reliability constraints.

This paper presents a novel architecture to solve two problems of existing FPGAs : the large delay and area due to complex programmable switch blocks, and the large area due to coarse-grain logic blocks that are underutilized to a great degree. A mesh-connected cellular array based on a bit-serial pipeline architecture is introduced to minimize complexity of switch blocks. A fine-grain logic block architecture with a functionality of a bit-serial adder is presented to minimize the number of inputs and outputs of the logic block since increase in the number of inputs and outputs directly increases the complexity of a switch block. For an area-efficient design, the logic block is implemented based on a hybrid of a programmable logic gate and a dedicated carry logic. The hybrid architecture allows us to use a small lookup table to implement the logic gate. Moreover, the carry logic uses a functional pass-gate that merges both logic and storage functions compactly. The performance of the fine-grain field-programmable VLSI (FPVLSI) is evaluated to be more than 2 times higher than that of a coarse-grain FPVLSI.

In this paper, we propose an optimal bit rate control algorithm which is fully compatible with MPEG-4 or H.263+. The proposed algorithm is designed to identify the optimal quantizer set through Lagrangian optimization when used for optimal bit allocation. To find the optimal quantizer set, we make use of the Viterbi algorithm in order to solve the dependency between quantization parameters of each macroblock due to the unique characteristics of MPEG-4 or H.263+. We set the Lagrangian cost function as a cost function of the Viterbi algorithm. We implement the proposed algorithm in MPEG-4 coders and compare its performance to the VM8 and optimal bit rate control algorithm, using independent quantization parameters in the circumstance of a low bit rate.

Some conventional beamformers require the direction of the desired signal. The performance of such beamformers can substantially be degraded even in the presence of small error on the directional information. In this letter, we propose a prefilter-type beamforming scheme robust to directional error by employing a simple compensator. The performance of the proposed scheme is verified by computer simulation.

This report describes a concrete method for realizing adiabatic charging reversible logic. First, we investigate the stabilization properties of a charge recycle regenerator using a switched capacitor circuit by SPICE simulation and an analytical method. In the N-step case, we proved that a step waveform is spontaneously generated. Next, for combinational logic, we propose an adiabatic charging binary decision diagram logic gate (AC-BDD) that uses this regenerator. The AC-BDD uses pass transistor logic based on a BDD, which is suitable for adiabatic logic. 8-bit AC-BDD multipliers were fabricated, and it is clarified that power consumption is reduced to 15% that of the same-rule-designed CMOS at 1 V and 1 MHz. Finally, we propose clocked energy reversible logic (CERL) that maintains the CMOS architecture for CMOS compatibility. CERL can reduce the clocked energy, which is used for charging the clock load capacitance, to 10% that of CMOS by using a power clock from the charge recycle regenerator.

In this paper, a sub-optimal Rake receiver combined with a Wiener Filter is investigated for use in an indoor environment. Inner-Chip-interference is dominant when the application is indoors, so the inner-chip-interference rejection function becomes critical for the receiver. Pilot symbols in each slot are used for channel estimation and weight calculation of Rake combining through Wiener Filter. Compared to conventional combining which uses maximum ratio combining, Wiener combining using IRC (Interference rejection combining) achieves better ICI (Inner-chip-Interference) rejection. This paper clarified that the sub optimal Rake receiver using Wiener Filter is 4 dB better than the conventional Rake receiver under the indoor application.

Reconfigurable logic circuitry has special importance because the popularity of Field Programmable Gate Arrays (FPGA) based applications. A reconfigurable logic based on FGMOS transistors, where a single stage can perform binary operations as well as state machines, is presented. The use of the proposed logic allows the integration of several stages into a single chip because their small area requirement, low voltage and low power characteristics.

In this paper, we present a hierarchical multi-chip architecture which employs fully digital and word-parallel associative memories based on Hamming distance. High capacity scalability is critically important for associative memories since the required database capacity depends on the various applications. A multi-chip structure is most efficient for the capacity scalability as well as the standard memories, however, it is difficult for the conventional nearest-match associative memories. The present digital implementation is capable of detecting all the template data in order of the exact Hamming distance. Therefore, a hierarchical multi-chip structure is simply realized by using extra register buffers and an inter-chip pipelined priority decision circuit hierarchically embedded in multiple chips. It achieves fully chip- and word-parallel Hamming distance search with no throughput decrease, additional clock latency of O(log P), and inter-chip wires of O(P) in a P-chip structure. The feasibility of the architecture and circuit implementation has been demonstrated by post-layout simulations. The performance has been also estimated based on measurement results of a single-chip implementation.

In this paper, we propose a formal method for detection of three automation surprises in human-machine interaction; a mode confusion, a refusal state, and a blocking state. The mode confusion arises when a machine is in a different mode from that anticipated by the user, and is the most famous automation surprise. The refusal state is a situation that the machine does not respond to a command the user executes. The blocking state is a situation where an internal event occurs, leading to change of an interface the user does not know. In order to detect these phenomena, we propose a composite model in which a machine and a user model evolve concurrently. We show that the detection of these phenomena in human-machine interaction can be reduced to a reachability problem in the composite model.

Many simulated annealing algorithms use the Cauchy neighbors for fast convergence, and the conventional method uses the product of n one-dimensional Cauchy distributions as an approximation. However, this method slows down the search severely as the dimension gets high because of the dimension-wise neighbor generation. In this paper, we analyze the orthogonal neighbor characteristics of the conventional method and propose a method of generating symmetric neighbors from the n-dimensional Cauchy distribution. The simulation results show that the proposed method is very effective for the search in the simulated annealing and can be applied to many other stochastic optimization algorithms.

Circuit techniques to realize stable recall operation and virtually unlimited read/program cycle operations in ferroelectric memory based nonvolatile (NV) SRAM composed of six-transistor and four-ferroelectric capacitor cells have been developed. Unlimited program cycle operation independent of ferroelectric material characteristics is realized by proper control of plate lines. Reliability evaluation results show that the developed memory cell has sufficient operation margin after stresses of temperature, fatigue, DC bias. Application of NV-SRAM to programmable logic devices has been discussed with a prototype of dynamically programmable gate arrays.

We study analysis of hybrid systems under incomplete knowledge. The class of hybrid systems to be considered is assumed to have the form of a rectangular hybrid automaton such that each constant in invariants and guards is given as a parameter. We develop a method based on symbolic computation that computes an approximation of the discrete behavior of the automaton. We also show an implementation on a constraint logic programming language.

We develop an algorithm for a controller design method for Max-Plus Linear (MPL) systems with selective parameters. Since the conventional algorithm we proposed requires high computational load when the prediction horizon is large, two methods for reducing the calculation time are proposed. One is based upon the branch-and-bound method, and the other is to reuse the optimal solution. The effectiveness of these two methods is confirmed through numerical simulation.

LOTOS parallel operator, which is a binary operator, is used to combine processes in order to express their concurrency. Unlike other LOTOS operators, various possibilities exist when combining processes by the parallel operator. If two processes are selected randomly for combining, the size of the composite intermediate process after combining may be large. In this paper, we propose an algorithm for selecting two processes out of three or more processes so that the size of the intermediate process is the smallest when combined by the parallel operator. Smaller size of an intermediate process means it takes less memory space which is very important in designing verification tools for systems or communication protocols specified in LOTOS.

Electronic Toll Collection (ETC), an application of Dedicated Short Range Wireless Communication (DSRC), had suffered from wrong operations due to multipath problems. To solve this problem, we proposed to apply a simple configured path determination scheme for the ETC system. The system consists of a vector network analyzer, low-noise amplifier, and X-Y positioner and achieves an automatic measurement of the spatial transfer function with emphasis on accurate measurement and reproducibility. For the reliable identification of the propagating paths, 3-D Unitary ESPRIT and SAGE algorithms were employed. Having developed the system, field experiments at the toll gate of the highway was carried out. In the measurements, we could determine many propagation paths so that the dominant propagation phenomena at the toll gate was identified. They included a ground-canopy twice reflected wave, which was a potential path that caused wrong operation. Consequently, their reflection coefficients and polarization characteristics were investigated. From the results, applicability of the path determination system for short range on-site measurement was confirmed.

This paper addresses the scheduling problem of a class of automated manufacturing systems with multiple resource requests. In the automated manufacturing system model, a set of jobs is to be processed and each job requires a sequence of operations. Each operation may need more than one resource type and multiple identical units with the same resource type. Upon the completion of an operation, resources needed in the next operation of the same job cannot be released and the remaining resources cannot be released until the start of the next operation. The scheduling problem is formulated by Timed Petri nets model under which the scheduling goal consists in sequencing the transition firing sequence in order to avoid the deadlock situation and to minimize the makespan. In the proposed genetic algorithm with deadlock-free constraint, Petri net transition sequence is coded and a deadlock detection method based on D-siphon technology is proposed to reschedule the sequence of transitions. The enabled transitions should be fired as early as possible and thus the quality of solutions can be improved. In the fitness computation procedure, a penalty item for the infeasible solution is involved to prevent the search process from converging to the infeasible solution. The method proposed in this paper can get a feasible scheduling strategy as well as enable the system to achieve good performance. Numerical results presented in the paper show the efficiency of the proposed algorithm.

This letter considers relationship between cyclic digital-to-analog converters (DACs) and iterated function systems (IFSs). We introduce the cyclic DACs as inverse systems of analog-to-digital converters in terms of one-dimensional maps. We then compare the DACs with a typical example of existing applications of IFSs: chaos game representation for analysis of DNA structures. We also present a simple test circuit of a DAC for Gray decoding based on switched capacitors and confirm the basic operation experimentally.

In this paper, an experimental result of complex refractive index of soda-lime glass at 30-GHz obtained by transmission method is presented at first. Secondly, a simple empirical formula of complex refractive index of soda-lime glass over frequency range from 0.1-GHz to 1000-GHz is derived using the present experimental result together with data previously reported in literatures by various researchers.

To improve the DS-CDMA signal transmission performance in a frequency-selective fading channel, the frequency-domain equalization (FDE) can be applied, in which simple one-tap equalization is carried out on each subcarrier component obtained by fast Fourier transform (FFT). Equalization weights for joint FDE and antenna diversity combining based on maximal ratio combining (MRC), zero-forcing (ZF), and minimum mean square error (MMSE) are derived. The conditional bit error rate (BER) is derived for the given set of channel gains in a frequency-selective multipath fading channel. The theoretical average BER performance is evaluated by Monte-Carlo numerical computation method using the derived conditional BER and is confirmed by computer simulation. Performance comparison between DS- and multi-carrier (MC)-CDMA both using FDE is also presented.