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14861-14880hit(21534hit)

  • Simple Extension of a Numerical Algorithm for Feedback Linearization to Multi-Input Nonlinear Systems

    Yu Jin JANG  Sang Woo KIM  

     
    LETTER-Systems and Control

      Vol:
    E86-A No:5
      Page(s):
    1302-1308

    Obtaining a linearizing feedback and a coordinate transformation map is very difficult, even though the system is feedback linearizable. It is known that finding a desired transformation map and feedback is equivalent to finding an integrating factor for an annihilating one-form for single input nonlinear systems. It is also known that such an integrating factor can be approximated using the simple C.I.R method and tensor product splines. In this paper, it is shown that m integrating factors can always be approximated whenever a nonlinear system with m inputs is feedback linearizable. Next, m zero-forms can be constructed by utilizing these m integrating factors and the same methodology in the single input case. Hence, the coordinate transformation map is obtained.

  • Output Feedback Passification of Nonlinear Systems Not in Normal Form

    Young I. SON  Hyungbo SHIM  Nam H. JO  Jin H. SEO  

     
    LETTER-Systems and Control

      Vol:
    E86-A No:5
      Page(s):
    1312-1315

    In this paper, the problem of output feedback passification for nonlinear systems is considered. Contrary to the conventional methodologies, our approach does not require the normal form representation of the system. Consequent advantages include that the system need not have a well-defined relative degree. In particular, we present a necessary and sufficient condition for output feedback passification without relying on the normal form. The proposed condition finally leads to an extension for a recent result when the system does have a normal form.

  • An Incremental Wiring Algorithm for VLSI Layout Design

    Yukiko KUBO  Shigetoshi NAKATAKE  Yoji KAJITANI  Masahiro KAWAKITA  

     
    LETTER

      Vol:
    E86-A No:5
      Page(s):
    1203-1206

    One of the difficulties in routing problem is in wirability which is to guarantee a physical connection of a given topological route. Wirability often fails since the width of a wire is relatively large compared with the size of modules. As a possible solution, this paper proposes an incremental wiring algorithm which generates wires net-by-net without overlapping other pre-placed circuit elements. The idea is to divide a wire into a series of rectangles and handles them as modules with additional constraints to keep the shape of the wire. The algorithm was implemented and experimented on a small instance to show its promising performance.

  • Priority-Based Wavelength Assignment Algorithm for Burst Switched WDM Optical Networks

    Xi WANG  Hiroyuki MORIKAWA  Tomonori AOYAMA  

     
    PAPER

      Vol:
    E86-B No:5
      Page(s):
    1508-1514

    Burst switched WDM optical networks are coming up as suitable network architectures for future Optical Internet backbones. However, the lack of optical processing capabilities results in increased burst blocking probability, which in turn lead to very limited network performance. Efficient contention resolution algorithm is therefore necessary. In this paper, we propose a distributed wavelength assignment algorithm named Priority-based Wavelength Assignment (PWA) for such networks. Each node selectively assigns wavelengths based on the wavelength priority information "learned" from its wavelength utilization history in a distributed manner. As the learning process progresses, nodes in the same part of the network tend to assign different wavelengths to avoid contentions. Simulation results show that the PWA can effectively reduce the blocking probability and increase the performance of burst optical networks compared to previous algorithms such as random assignment.

  • Programmable Electrooptic Wavelength Filter Using Cascaded Mode Converters

    Hideaki OKAYAMA  

     
    PAPER

      Vol:
    E86-C No:5
      Page(s):
    777-780

    A new device structure for electrooptic tunable wavelength filter is reported. Finger electrode electrooptic mode converters are placed on an optical waveguide. The drive voltage amplitude is changed along the propagation distance with a sinusoidal function. Changing the spatial period of sinusoidal voltage results in wavelength tuning. Structure uses interleaved mode converter groups generating cosine and sine function mode conversion strengths.

  • B-Ternary Asynchronous Digital System under Relativity Delay

    Yasunori NAGATA  Masao MUKAIDONO  

     
    PAPER-Computer System Element

      Vol:
    E86-D No:5
      Page(s):
    910-919

    Some of the recent digital systems have a serious clock skew problem due to huge hardware implementation and high-speed operation in VLSI's. To overcome this problem, clock distribution techniques and, more notably, asynchronous system design methodologies have been investigated. Since the latest asynchronous digital systems use two-rail logic with two-phase data transfer manner, more than two-fold hardware is required in comparison with the synchronous system. In this article, we present a design of asynchronous digital system which is based on B-ternary logic that can process binary data. The system which is based on speed-independent mode consists of data-path and its controller. Then we provide B-ternary two-phase binary data processing in the data-path and its control procedure with hand-shake protocol. To implement the system some functional elements are presented, that is, a ternary-in/binary-out register with request/acknowledge circuits and a control unit. These functional elements are fabricated with ternary NOR, NAND, INV gates and ternary-in/binary-out D-FF (D-elements). The B-ternary based asynchronous circuit has less interconnections, achives race-free operations and makes use of conventional binary powerful design tools. Particularly, we extend the speed-independent delay model to relativity delays in order to reduce hardware overhead of checking memory stability in the system. As a concrete example, a carry-completion type asynchronous adder system is demonstrated under extended speed-independent mode to show the validity of the extension.

  • An Algorithm for Solving the Minimum Vertex Ranking Spanning Tree Problem on Interval Graphs

    Shin-ichi NAKAYAMA  Shigeru MASUYAMA  

     
    PAPER

      Vol:
    E86-A No:5
      Page(s):
    1019-1026

    The minimum vertex ranking spanning tree problem is to find a spanning tree of G whose vertex ranking is minimum. This paper proposes an O(n3) time algorithm for solving the minimum vertex ranking spanning tree problem on an interval graph.

  • Reconfigurable Onboard Processing and Real-Time Remote Sensing

    John A. WILLIAMS  Anwar S. DAWOOD  Stephen J. VISSER  

     
    PAPER

      Vol:
    E86-D No:5
      Page(s):
    819-829

    In this paper we present reconfigurable computing as a compelling choice of computing platform for real-time, onboard processing for satellite applications. In particular, we discuss the use of reconfigurable computing in the context of a real-time remote sensing system, providing motivation for such a system and describing attributes of reconfigurable computing that support it as the technology of choice. The High Performance Computing (HPC-I) payload, designed and developed for the Australian scientific satellite FedSat, is introduced as a demonstration of onboard processing in space using reconfigurable logic. We present an overview of the real-time remote sensing system architecture, and describe the design and implementation of three remote sensing algorithms in HPC-I for cloud masking, wildfire detection and volcanic plume detection. Finally, results from simulation and testing are presented which show very promising performance in terms of data throughput and detection capabilities.

  • A 10 Gbase Ethernet Transceiver (LAN PHY) in a 1.8 V, 0.18 µm SOI/CMOS Technology

    Tsutomu YOSHIMURA  Kimio UEDA  Jun TAKASOH  Harufusa KONDOH  

     
    PAPER-Design Methods and Implementation

      Vol:
    E86-C No:4
      Page(s):
    643-651

    In this paper, we present a 10 Gbase Ethernet Transceiver that is suitable for 10 Gb/s Ethernet applications. The 10 Gbase Ethernet Transceiver LSI, which contains the high-speed interface and the fully integrated IEEE 802.3ae compliant logics, is fabricated in a 0.18 µm SOI/CMOS process and dissipates 2.9 W at 1.8 V supply. By incorporating the monolithic approach and the use of the advance CMOS process, this 10 GbE transceiver realizes a low power, low cost and compact solution for the exponentially increasing need of broadband network applications.

  • Convergence of Alternative C-Means Clustering Algorithms

    Kiichi URAHAMA  

     
    LETTER-Pattern Recognition

      Vol:
    E86-D No:4
      Page(s):
    752-754

    The alternative c-means algorithm has recently been presented by Wu and Yang for robust clustering of data. In this letter, we analyze the convergence of this algorithm by transforming it into an equivalent form with the Legendre transform. It is shown that this algorithm converges to a local optimal solution from any starting point.

  • Comparison of the Total Inter-Carrier Interference Caused by the Doppler Effect in OFDMA and a Proposed Hybrid CDMA-OFDMA System

    Luis LOYOLA  Tetsuya MIKI  

     
    PAPER-Wireless Communication Technology

      Vol:
    E86-B No:4
      Page(s):
    1256-1264

    Time variations of the wireless channel cause Inter-Carrier Interference (ICI) between different subcarriers in an OFDM system. In a highly mobile environment this interference may become so high that it degrades up to unacceptable levels the communication channel. In this paper, firstly we obtain a simplified expression for the total ICI experienced by every subcarrier in an OFDMA system. Unlike other previous works, the result establishes an explicit and useful relation between the ICI on each subcarrier and the speed of the rest of the terminals in the system. Then, by means of a mathematical analysis we extend the scope of that expression to a hybrid system in which OFDMA and CDMA are combined. Using the good autocorrelation and cross-correlation properties provided by Gold-sequences we propose a Gold-Code-based CDMA-OFDMA transmission technique for the asynchronous uplink channel. We show that the proposed method can reduce the total ICI and potentially increase the capacity of the system in comparison to a conventional OFDMA system.

  • Load Fluctuation-Based Dynamic File Allocation with Cost-Effective Mirror Function

    Jun TAKAHASHI  Akiko NAKANIWA  Yasutomo ABE  Hiroyuki EBARA  Hiromi OKADA  

     
    PAPER-Network

      Vol:
    E86-B No:4
      Page(s):
    1317-1326

    Mirroring of network servers has been considered to be effective for load balancing. However, the cost of setting up new mirror servers is enormously high. In this paper, we propose a dynamic file allocation model with a simple mirroring function for handling significant changes of network traffic in the Internet. According to the load fluctuation, we can dynamically reallocate files using this model. We show that our model accomplishes satisfactory performance and reduces cost by adding a simple mirroring function to all existent servers instead of setting up mirror servers afresh.

  • Dynamic Channel Assignment and Reassignment for Exploiting Channel Reuse Opportunities in Ad Hoc Wireless Networks

    Chih-Yung CHANG  Po-Chih HUANG  Chao-Tsun CHANG  Yuh-Shyan CHEN  

     
    PAPER-Wireless Communication Technology

      Vol:
    E86-B No:4
      Page(s):
    1234-1246

    In Ad Hoc networks, communication between a pair of hosts uses channel resources, such that the channel cannot be used by the neighboring hosts. A channel used by one pair of hosts can be reused by another pair of hosts only if their communication ranges do not overlap. Channels are limited resources, accounting for why exploiting channel reuse opportunities and enhancing the channel utilization is essential to increasing system capacity. However, exploiting channel reuse opportunities may cause a co-channel interference problem. Two pairs of communicating hosts that use the same channel may gradually move toward to each other. A channel reassignment operation must be applied to these hosts to maintain their communication. This investigation presents a channel assignment protocol that enables the channel resources to be highly utilized. Following this protocol, a channel reassignment protocol is also proposed to protect the communicating hosts from co-channel interference caused by mobility. The proposed reassignment protocol efficiently reassigns a new available channel to a pair of hosts that suffers from co-channel interference. The performance of the proposed protocols is also examined. Experimental results reveal that the proposed protocols enable more hosts to communicate simultaneously and prevent their communication from failing.

  • GAHA and GAPA: Two Link-Level Approaches for Supporting Link Asymmetry in Mobile Ad Hoc Networks

    Dongkyun KIM  Chai-Keong TOH  Yanghee CHOI  

     
    PAPER-Terrestrial Radio Communications

      Vol:
    E86-B No:4
      Page(s):
    1297-1306

    Existing routing protocols for mobile ad hoc networks assume that all nodes have the same transmission range. In other words, the mobile ad hoc network has symmetric links, which means that two neighboring nodes A and B are within the transmission range of one another. However, since nodes consume battery power independently according to their computing and communication load, there exist asymmetric links, which means that node A is within node B's transmission range, but not vice versa. In this paper, two approaches are presented to support routing in the existence of asymmetric links: GAHA (GPS-based Hop-by-hop Acknowledgment) and GAPA (GPS-based Passive Acknowledgment) schemes. Both GAHA and GAPA can be applied to any routing protocols by utilizing GPS (Global Positioning System) location information. Simulation results reveal that both GAHA and GAPA protocols cope well in the presence of asymmetric wireless links and nodes' mobility.

  • Frequency Offset Estimation Technique for OFDM Transmission System

    Hyoung-Kyu SONG  Mi-Jeong KIM  

     
    LETTER-Wireless Communication Technology

      Vol:
    E86-B No:4
      Page(s):
    1435-1438

    The OFDM technique has recently received considerable attention in the fields of wireless LAN communication systems. It is accompanied with many practical issues and one major issue is synchronization. In this letter, we propose a frequency offset estimation technique for OFDM system. The proposed frequency offset estimator employing interpolation technique in the frequency domain has a simple structure and good performance.

  • Human Face Detection via Characterized Convex Regional Relationship in Color Images

    Chang-Woo PARK  Euntai KIM  Mignon PARK  

     
    LETTER-Image Processing, Image Pattern Recognition

      Vol:
    E86-D No:4
      Page(s):
    759-762

    In this letter, we propose a new method to detect faces in color images based on the characterized convex regional relationship. We detect skin and hair likeness regions using the derived skin and hair color models and the convex skin likeness and hair likeness regions are adopted as the characteristic convex regions. Finally, human faces can be detected via their intersection relationship. The proposed algorithm can accomplish face detection in an image including not only single face but also multi-faces and also detect deformed faces efficiently. To validity the effectiveness of the proposed method, we make experiments with various cases.

  • Reducing Memory System Energy by Software-Controlled On-Chip Memory

    Masaaki KONDO  Hiroshi NAKAMURA  

     
    PAPER-Architecture and Algorithms

      Vol:
    E86-C No:4
      Page(s):
    580-588

    In recent computer systems, a large portion of energy is consumed by on-chip cache accesses and data movement between cache and off-chip main memory. Reducing these memory system energy is indispensable for future microprocessors because power and thermal issues certainly become a key factor of limiting processor performance. In this paper, we discuss and evaluate how our architecture called SCIMA contributes to energy saving. SCIMA integrates software-controllable memory (SCM) into processor chip. SCIMA can save total memory system energy by using SCM under the support of compiler. The evaluation results reveal that SCIMA can reduce 5-50% of memory system energy and still faster than conventional cache based architecture.

  • A 2-Approximation Algorithm 2-ABIS for 2-Vertex-Connectivity Augmentation of Specified Vertices in a Graph

    Makoto TAMURA  Satoshi TAOKA  Toshimasa WATANABE  

     
    PAPER

      Vol:
    E86-A No:4
      Page(s):
    822-828

    The 2-vertex-connectivity augmentation problem for specified vertices (2VCA-SV) is defined as follows: Given an undirected graph G=(V,E), a subgraph G0=(V,E') of G, a specified set of vertices S V and a weight function w:E R^+ (nonnegative real numbers), find a set E" E-E' with the minimum total weight, such that G0+E"=(V,E' E") has at least two internally disjoint paths between any pair of vertices in S. In this paper, we propose an O(|V||E|+ |V|2 log |V|) time algorithm 2-ABIS, whose performance ratio is 2 (3, respectively), for 2VCA-SV if G0 has a connected component containing S (otherwise).

  • A Hybrid On-Demand Content Delivery Scheme Employing Modified Pyramid Broadcasting

    Tomoaki KUMAGAI  Hiroshi SAITO  

     
    PAPER-Media Compound Methods

      Vol:
    E86-B No:4
      Page(s):
    1399-1411

    This paper proposes a hybrid on-demand content delivery scheme employing modified pyramid broadcasting. Our scheme delivers a fixed-sized head portion of the video content to each client individually via an individual channel and the remaining portion via multiple broadcasting channels by using a modified form of pyramid broadcasting. The feature of this scheme is that it can be used together with forward error correction using block coding. Therefore, it can deliver high-quality content upon request with high network bandwidth efficiency even if data containers, such as Ethernet frames, are lost in the IP network. This is not possible with conventional schemes. Evaluation results show that its network bandwidth performance is still excellent even though it supports well-known FEC schemes using block coding.

  • OAG*: Improved Ordered Attribute Grammars for Less Type 3 Circularities

    Shin NATORI  Katsuhiko GONDOW  Takashi IMAIZUMI  Takeshi HAGIWARA  Takuya KATAYAMA  

     
    PAPER-Theory of Automata, Formal Language Theory

      Vol:
    E86-D No:4
      Page(s):
    673-685

    Ordered attribute grammars (OAGs for short) are a useful class of attribute grammars (AGs). For some attribute grammars, even though they are not circular, OAG circularity test reports that they are not ordered and fails to generate attribute evaluators because some approximation introduces circularities (called type 3 circularities in this paper). First we discuss that it is sometimes difficult for programmers to eliminate type 3 circularities by hand. Second, to reduce this difficulty, we propose a new AG class called OAG* that produces less type 3 circularities than OAG while preserving the positive characteristic of OAG. OAG* uses a global dependency graph GDS that provides a new approximation algorithm. We obtained good results with our experimental implementation of OAG*. It is shown that OAG* is different from the existing GAG and Eli/Liga systems. Finally, two combinations of Eli/Liga and OAG* are provided.

14861-14880hit(21534hit)