Server performance is a major issue in improving the overall performance of the World Wide Web (WWW). This article introduces a dynamic mirroring-based approach to improve WWW servers' performance. In contrast to static mirroring, where mirror servers are allocated statically, our mirror servers' setup is driven by network traffic measurement. Performance in terms of latency is inferred from a queuing model. According to this model we show that latency of an overloaded server can be tuned by delegating a portion of the load to a cooperative mirror server. Cost is evaluated by the amount of load hosted by the mirror servers. The goal is then to keep the latency within a tolerable threshold, while minimizing the delegated load. This problem is formulated as a constrained optimization problem where the task is to assign a portion of load corresponding to each document to each mirror server. As the result of this work, we will have a balanced load among the servers, and a smoother traffic along the Internet, as well. Empirical results show that this approach can guarantee to maintain the performance while showing a significant decrease in the amount of load transferred to the mirror servers.

This paper investigates multiple-valued code-division multiple access (MV-CDMA) techniques and circuits for intra/inter-chip communication to achieve efficient data transmission in VLSI systems. To address the problems caused by interconnection complexity, we transmit multiplexed signals inside LSI systems employing pseudo-random orthogonal m-sequences as information carriers. A new class of multiple-valued CDMA techniques for intra-chip communication is discussed to demonstrate the feasibility of eliminating co-channel interference caused by a propagation delay of signals, e.g., clock skew. This paper describes the circuit configuration and performance evaluation of MV-CDMA systems for intra-chip communication. We first explain the principle of MV-CDMA technique, and then propose a bidirectional current-mode CMOS technique to realize compact correlation circuits for CDMA. Finally, we show the Spice and MATLAB simulation results of MV-CDMA systems, which indicate the excellent capabilities of eliminating co-channel interference.

A space-time (ST) receiver is proposed for multiple access interference (MAI) and narrowband interference (NBI) suppression, and multipath diversity reception in wireless multi-carrier CDMA communications incorporating antenna arrays. The scheme involves three stages. First, an adaptive matched filter is attached to each finger at each antenna to combat the MAI. Second, an adaptive beamformer is constructed for each finger which provides effective reception of the signal of interest (SOI) and suppression of time-varying NBI. Finally, beamformer output data from different fingers are combined to capture the signal multipath components coherently. The proposed ST receiver is shown to perform reliably under strong interference, and outperform the ST MMSE receiver with pilot symbols aided channel estimation.

This paper proposes an asymmetric bandwidth access network based on super-dense wavelength-division multiplexing (SD-WDM) technologies; the network guarantees 100 Mbps upstream and 1 Gbps downstream bandwidth to each user and supports wide-area transmission. The network minimizes operation and administration costs by consolidating switching equipment, as well as minimizing wavelength monitoring/stabilization functions by employing two technologies; the optical multi-carrier supply module (OCSM) for creating downstream signals and the directly modulated spectrum slicing scheme for creating upstream signals. After describing the configuration and features of the presented network, we demonstrate a bandwidth guaranteed network for each of 64 users with 100 Mbps upstream and 1 Gbps downstream bandwidth. The network provides 10-km access lines with under 7-dB loss from users to the access node and a 120-km metro-loop transmission line with under 25-dB loss from the access node to the center node.

Problems concerning a phase-locked loop (PLL) fabricated by a deep-sub-micron process were investigated, and a high-speed self-calibration technique for tuning a voltage-controlled oscillator (VCO) frequency range automatically was developed. The self-calibration technique can measure VCO frequency in short time by comparing intervals between a PLL reference and a VCO output. Furthermore, a loop-filter bypassing method was also used to change the calibration frequency in short time. At 0.7 V and 200 MHz, the prototype PLL has a calibration time of 1.4 µs and a total settling time of 10 µs, which are adequate for microprocessor applications. Moreover, the PLL has a cycle-to-cycle jitter of 142 ps and a power consumption of 470 µW.

A voltage-mode universal biquadratic filter using single current-feedback amplifier (CFA), two capacitors and three resistors is presented. The new circuit has four inputs and one output and can realize all the standard filter functions, that is, lowpass, bandpass, highpass, notch and allpass filters, without changing the circuit topology. The use of only one current-feedback amplifier simplifiers the configuration.

In this paper, a new voice personality transformation algorithm which uses the vocal tract characteristics and pitch period as feature parameters is proposed. The vocal tract transfer function is divided into time-invariant and time-varying parts. Conversion rules for the time-varying part are constructed by the classified-linear transformation matrix based on soft-clustering techniques for LPC cepstrum expressed in KL (Karhunen-Loève) coefficients. An excitation signal containing prosodic information is transformed by average pitch ratio. In order to improve the naturalness, transformation on the excitation signal is separately applied to voiced and unvoiced bands to preserve the overall spectral structure. Objective tests show that the distance between the LPC cepstrum of a target speaker and that of the speech synthesized using the proposed method is reduced by about 70% compared with the distance between the target speaker's LPC cepstrum and the source speaker's. Also, subjective listening tests show that 60-70% of listeners identify the transformed speech as the target speaker's.

An image halftoning technique that uses a simple GA has proven to be effective generating bi-level halftone images with quality higher than conventional techniques. Many devices are designed to handle more than two halftone levels and a GA based multi-level halftoning technique is desirable. In this paper we extend the bi-level halftoning technique to generate multi-level halftone images. Also we introduce an improved GA (GA-SRM) into the proposed multi-level halftoning technique. Experimental results show that the proposed technique can effectively generate high quality multi-level halftone images and that the inclusion of GA-SRM substantially contributes reducing memory usage and accelerating image generation.

Since the penetration of VSAT services is rapidly increasing, more earth stations will operate around airports than is currently true. This makes it essential to evaluate accurately and efficiently the impairment of received signals due to blockage by aircraft. This paper proposes developing an aircraft model using a thin, planar polygon to represent the aircraft projection and to apply GTD with corner diffraction terms. The effectiveness and applicability of the method is then examined numerically. It is demonstrated that the results measured in the Ku-band around two airports are a good match with the numerical simulations even when the distance between the aircraft and the stations is small.

Most of the QoS-based routing schemes proposed so far focus on improving the performance of individual service classes. In a multi-class network where high priority QoS traffic coexists with best-effort traffic, routing decision for QoS sessions will have an effect on lower ones. A mechanism that allows dynamic sharing of link resources among multiple classes of traffic is needed. In this paper we propose a multi-class routing algorithm based on inter-class sharing resources among multiple class of traffic. Our algorithm is based on the concept of "the virtual residual bandwidth," which is derived from the real residual bandwidth. The virtual residual bandwidth is greater than the residual bandwidth when the load of lower priority traffic is light, and smaller when the load of lower priority traffic is heavy. The idea of our approach is simple since the routing algorithm for individual traffic doesn't change, but the only change is the definition of the link cost. We demonstrate through some extensive simulations the effectiveness of our approach when the best effort distribution is uneven and when its load is heavy. Also better performance is noticed when using topology with large number of alternative paths.

In this paper, we present an efficient VLSI architecture for the stand-alone application of a speech recognition system based on discriminative Bayesian neural network (DBNN). Regarding the recognition phase, the architecture of the Bayesian distance unit (BDU) is constructed first. In association with the BDU, we propose a template-serial architecture for the path distance accumulation to perform the recognition procedure. A corresponding architecture is also developed to accelerate the discriminative training procedure. It contains the intelligent look-up table for the sigmoid function. In comparison to the traditional one-table method, the memory size reduces drastically with only slight loss of accuracy. Combining the proposed hardware accelerators with the cost efficient programmable core, we took the most out of both programmable and application-specific architectures, including performance, design complexity, and flexibility.

Adaptive optimization of the notch bandwidth of a lattice-based adaptive infinite impulse response (IIR) notch filter is presented in this paper. The filter is used to improve the performance of a direct sequence spread spectrum (DSSS) binary phase shift keying (BPSK) communication system by suppressing a narrow-band interference at the receiver. A least mean square (LMS) algorithm used to adapt the notch bandwidth coefficient to its optimum value which corresponds to the maximum signal to noise ratio (SNR) improvement factor is derived. Bit error rate (BER) improvement gained by the DSSS communication system using the filter with the optimized notch bandwidth is also shown. Computer simulation results are compared with those obtained analytically to demonstrate the validity of theoretical predictions for various received signal parameters.

A quasi-periodic signal is a periodic signal with period and amplitude variations. Several physiological signals, including the electrocardiogram (ECG), can be treated as quasi-periodic. Vector quantization (VQ) is a valuable and universal tool for signal compression. However, compressing quasi-periodic signals using VQ presents several problems. First, a pre-trained codebook has little adaptation to signal variations, resulting in no quality control of reconstructed signals. Secondly, the periodicity of the signal causes data redundancy in the codebook, where many codevectors are highly correlated. These two problems are solved by the proposed codebook replenishment VQ (CRVQ) scheme based on a bar-shaped (BS) codebook structure. In the CRVQ, codevectors can be updated online according to signal variations, and the quality of reconstructed signals can be specified. With the BS codebook structure, the codebook redundancy is reduced significantly and great codebook storage space is saved; moreover variable-dimension (VD) codevectors can be used to minimize the coding bit rate subject to a distortion constraint. The theoretic rationale and implementation scheme of the VD-CRVQ is given. The ECG data from the MIT/BIH arrhythmic database are tested, and the result is substantially better than that of using other VQ compression methods.

It is widely known that the family of projection filters includes the generalized inverse filter, and that the family of parametric projection filters includes parametric generalized projection filters. However, relations between the family of parametric projection filters and constrained least squares filters are not sufficiently clarified. In this paper, we consider relations between parameter estimation and image restoration by these families. As a result, we show that the restored image by the family of parametric projection filters is a maximum penalized likelihood estimator, and that it agrees with the restored image by constrained least squares filter under some suitable conditions.

Quality of service (QoS) technology has been implemented and started to be applied to new applications on the next-generation Internet. However, as new applications have many kinds of features and requirements, some additional features should be added to current QoS control technology. For example, they require a definition of a single policy to operate QoS control in the management domain consistently and efficiently. Policy definition for transport layer in a domain and among domains is being discussed at IETF to set a standard process, however detailed policy corresponding to the application or contents information according to the application semantics has not been discussed. Therefore we developed QoS policy control mechanism using metadata which is defined as a structured data according to the application semantics. Though metadata and transport mechanism can be located into quite different positions in the concept of network layers, we made them successfully collaborated by defining meta policy. In this paper, we describe our approach to define a meta policy based on the requirements and information contents from the application as a high level layer concept to be able to classify the network behavior. Our approach enables to multiple QoS control and collaboration among domains. We also report of the activities in IETF and ITU-T.

This paper describes low-power and low-voltage analog circuit techniques applicable to deep sub-micron LSIs in baseband and RF signal processing. The trends indicate that reductions in the supply voltage are inevitable, that power dissipation will not become sufficiently low, and that performance will improve continuously. Some circuit techniques currently being used to achieve these goals are reviewed. Next, three trial approaches are introduced. The first of these is a 1 V operational video-speed CMOS sample-and-hold IC. The second is a 1 V operational high-frequency CMOS VCO circuit. Finally, a step-down DC-DC converter IC with a 1 V output and a greater than 80% power efficiency is introduced. These approaches prove that the low-power and low-voltage operation of analog circuits can be realized without sacrificing performance.

This paper presents data coding techniques for a stable single-bit noise-shaping quantizer, which has a cascade structure of a multi-bit ΣΔ modulator and a binary interpolator. The binary interpolator chooses a pre-optimized binary vector for each input sample and successively generates the chosen binary vector as an output bit stream. The binary vectors can have different lengths. The paper also proposes two methods to evaluate and bound output errors of a binary interpolator. A multi-bit ΣΔ modulator is designed to cause no overload for all possible input signals whose amplitudes are bounded to a specified level, and thus the ΣΔ modulator rigorously guarantees the stability condition. In design examples, we have evaluated Signal-to-Noise and Distortion Ratios (SNDRs) and noise spectra and then confirmed that our stable quantizers can sharply shape output noise spectra.

Embedded-DRAM (eDRAM) power-energy estimation model is proposed for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improves the accuracy of the conventional SRAM power-energy models. The power-energy estimation using SSBA model shows 95% accuracy compared with the transistor level power simulation for three fabricated eDRAMs. The SSBA model combined with the high-level simulator provides fast and accurate system level power-energy estimation of eDRAM.

MOSFETs can be used as capacitors, but its capacitance can vary by 5 to 7 times as its terminal voltage varies. To reduce the voltage dependence of the capacitance, this paper proposed two types of devices: one is called accumulation MOSFET (AMOS) and the other is formed by two conventional PMOS connected in anti-parallel. These two devices are readily available in the standard digital CMOS processes. The proposed capacitors were implemented in three different CMOS processes. The measured results show that the capacitances of both devices have less voltage dependence than a single PMOS. The voltage dependence of the AMOS capacitance can be as small as 17%. The minimum capacitance per unit area of the AMOS is 1.8 times that of the double-poly capacitor in an analog/mixed-mode CMOS process. To verify the usefulness of these two types of capacitors, they are used as compensation capacitors in a conventional two-stage amplifier. The measured results show that the amplifier compensated by the AMOS capacitor has little variation (6%) of the unity-gain frequency over the input common-mode range. Due to its smaller die area and cheaper digital process, AMOS can be used as compensation capacitor without resorting to more expensive analog process.

This paper presents a novel low-energy memory design technique based on variable analysis for on-chip data memory (RAM) in application-specific systems, which called VAbM technique. It targets the exploitation of both data locality and effective data width of variables to reduce energy consumed by data transfer and storage. Variables with higher access frequency and smaller effective data width are assigned into a smaller low-energy memory with fewer bit lines and word lines, placed closer the processor. Under constraints of the number of memory banks, VAbM technique use variable analysis results to perform allocating and assigning on-chip RAM into multiple banks, which have different size with different number of word lines and different number of bit lines tailored to each application requirements. Experimental results with several real embedded applications demonstrate significant energy reduction up to 64.8% over monolithic memory, and 27.7% compared to memory designed by memory banking technique.