A novel cumulant based MUSIC like DOA estimation algorithm for multicarrier modulation has been proposed in this paper. While the conventional MUSIC algorithm is not applicable to a correlation matrix calculated from received signals transmitted over the different carriers, the proposed algorithm can estimate the DOA of the signals with multicarrier modulation. The proposed algorithm does not require the sensor array responses for the frequency range of the interest and the initial phases of the carriers. With the proposed algorithm the number of signals whose DOA are estimated can be increased and the accuracy of the DOA estimation can be improved by employing larger number of carriers.

In recent years, several global network systems using non-stationary satellites have been proposed. Some of them are announced to start services within years. We also have several experimental systems with stratospheric aircrafts. In the future, the radio communication system using stratospheric aircrafts will be one of the promising media for personal communications. The question of how to establish the optimal communication under such circumstance seems to be still open. In this paper, performance evaluations of wireless communication systems using LEO satellites and stratospheric aircrafts are proposed. We will show some proper communication parameters to improve competence of mobile communication in the such systems as well.

This paper implements some new techniques to analyze the light beam scattering from a magneto-optical (MO) disk using the three-dimensional finite-difference time-domain (FDTD) method. The anisotropic FDTD update equations are implemented to calculate the propagation of a coherent monochromatic light in the MO material. An anisotropic absorbing boundary condition based on Berenger's perfectly matched layer (PML) concept is also developed. The Gaussian incident light beam is introduced into FDTD computation region exactly by using equivalent electric and magnetic currents. The scattering pattern of light beam from the MO disk is computed and in part compared with that obtained by using the boundary element method. The scattering patterns by the circular recording bit of different radius are calculated to indicate the optimum radius of the recording bit.

Consider a random digraph G=(V,A), where |V|=n and an arc (u,v) is present in A with probability p(n) independent of the existence of the other arcs. We discuss the expected number of vertices reachable from a vertex, the expected size of the transitive closure of G and their related topics based on the properties of reachability, where the reachability from a vertex s to t is defined as the probability that s is reachable to t. Let γn,p(n) denote the reachability s to t (s) in the above random digraph G. (In case of s=t, it requires another definition. ) We first present a method of computing the exact value of γn,p(n) for given n and p(n). Since the computation of γn,p(n) by this method requires O(n3) time, we then derive simple upper and lower bounds γn,p(n)U and γn,p(n)L on γn,p(n), respectively, and in addition, we give an upper bound n,p(n) on γn,p(n)U, which is easier to analyze but is still rather accurate. Then, we discuss the asymptotic behavior of n,p(n) and show that, if p(n)=α/(n-1), limnn,p(n) converges to one of the solutions of the equation 1-x-e-α x=0. Furthermore, as for (n) and (n), which are upper bounds on the expected number of reachable vertices and the expected size of the transitive closure of G, resp. , it turns out that limn(n) =α/(1-α) if p(n)=α/(n-1) for 0<α<1; otherwise either 0 or , and limn(n)=α if p(n)=α/(n-1)2 for α0; otherwise either 0 or .

This paper proposes a high-level synthesis system for datapath design of digital processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.

A Pragmatic Trellis Coded MPSK on a Rayleigh fading channel is analyzed. This scheme allows bandwidth expansion ratio to be varied aiming at an optimization between complexity of the system design and improvement of coding gain. In order to vary the bandwidth expansion ratio, a punctured convolutional code is used. The performance of the proposed TC-2mPSK on a Rayleigh fading channel is theoretically analyzed. In the test examples, the BER performances of TC-QPSK and TC-8PSK are evaluated by theoretical analyses and computer simulations at the encoder parameters of K3 and r3/4. The results show that the proposed scheme can attain better performance not only over the uncoded scheme but over the conventional Pragmatic TCM.

In many embedded systems, a significant amount of power is consumed for off-chip driving because off-chip capacitances are much larger than on-chip capacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and two scheduling algorithms are presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithms.

This paper proposes a new flexible hardware model for pipelined design optimization. Using together with an RTL floorplanner, the flexible hardware model makes accurate and fine design space exploration possible. It is quite effective for deep submicron technology since estimation at high level has become a difficult problem and the design tuning at lower level of abstraction makes up the full design optimization task. The experimental results show that our approach reduces the slack time in the pipeline stages then achieves higher performance with a smaller area.

Analysis of frequency-dependent lossy transmission lines is very important for designing the high-speed VLSI, MCM and PCB. The frequency-dependent parameters are always obtained as tabulated data. In this paper, a new curve fitting technique of the tabulated data for the moment matching technique in the interconnect analysis is presented. This method based on Chebyshev interpolation enhances the efficiency of the moment matching technique.

A fuel cell energy system is under development for supply of generated electrical energy to telecommunications equipment. It is a cogeneration system; the heat energy recovered is used to cool the telecommunications equipment. For this system, a method is described for controlling a new DC interconnection converter. Its DC interconnection characteristics are also discussed. The new converter controls its input current to the fuel cell rated current at maximum and can operate stably even when the fuel cell voltage decreases. This allows good DC interconnection characteristics to be obtained in both the steady state and the transient state.

The importance of technology retargeting for hard IPs is getting increased. However, recent advances in process technologies make layout reuse too complicated to be done by conventional compactors. As an efficient approach, this paper proposes a flexible layout abstraction model and a new layout synthesis algorithm. The synthesis algorithm provides a concurrent procedure of detailed wiring, compaction, and transistor layout generation by using a scan line to get better layout results than conventional compactors. We have applied this method to the technology retargeting of actual cell layouts and have achieved quite good results comparable to hand-crafted designs.

The mapping from a global routing to a feasible detailed routing in a number of 2D array routing structures has been shown to be an NP-complete problem. These routing structures include the Xilinx style routing architecture, as well as architectures with significantly higher switching flexibility. In response to this complexity, a different class of FPGA routing structures called Greedy Routing Architectures (GRAs) have been proposed. On GRAs, optimally routing each switch box, in a specified order, leads to an optimal chip routing. Because routing each switch box takes polynomial time, the mapping problem on GRAs can be solved in polynomial time. In particular, an H-tree GRA with W2+2W switches per switch box (SpSB) and a 2D array GRA with 4W2+2W SpSB have been proposed. In this paper, we improve on these results by introducing an H-tree GRA with W2/2+2W SpSB and a 2D array GRA with 3.5W2+2W SpSB. These new GRAs have the same desirable mapping properties of the previously described GRAs, but use fewer switches.

Conventional approach for frequency estimation usually assume a single tone without data modulation. In many applications such an assumption, realized by using either a separate pilot beacon or synchronization preamble is not feasible. This paper deals with frequency estimation of phase-modulated carriers in the absence of timing information and known data pattern. We introduce new frequency estimators that are based on the generalized maximum likelihood principle. The communication channels under consideration include both additive white Gaussian noise (AWGN) channels and correlated Rician fading channels. For the latter class, we distinguish between the case when the fading (amplitude) process is tracked and that when it is not tracked.

A novel zero-voltage-switched half-bridge converter is proposed. This converter achieves the zero-voltage switching while maintaining a constant frequency PWM control. Then the power conversion of high efficiency and low noise is realized at a higher switching frequency. In the experiment, a high efficiency of 83% is achieved for a low output voltage of 3.3 V, an output current of 30 A, and an input-voltage range of 200 to 400 V at the switching frequency of 400 kHz.

This paper reports on an Intelligent CASE tool, applicable in a structured programming phase, or from detailed design to coding. This is automation of the bottom level in the hierarchical design process of detailed design and coding, where the largest man-hours are consumed. The main idea is that human designers use a CASE tool for the initial design of a software system, and the design knowledge is automatically acquired from the structured charts and stored in the knowledge base. The acquired design knowledge may be reused in designs. By reusing it, a similar software system may be designed automatically. It has been shown that knowledge acquired in this way has a Logarithmic Learning Effect. Based on this, a quantitative evaluation of productivity is made. By accumulating design experiences (e. g. 10 times), more than 80% of the detailing designs are performed automatically, and productivity increases by up to 4 times. This tool features universality, an essentially zero start-up cost for automatic design, and a substantial increase in software productivity after enough experiences have been accumulated. This paper proposes a new basic idea and its implementation, a quantitative evaluation applying techniques from Industrial Engineering, which proves the effectiveness of the proposed system.

Call tracking data contains a calling address, called address, service type, and other useful attributes to predict a customer's calling activity. Call tracking data is becoming a target of data mining for telecommunication carriers. Conventional data-mining programs control the number of association rules found with two types of thresholds (minimum confidence and minimum support), however, often they generate too many association rules because of the wide variety of patterns found in call tracking data. This paper proposes a new method to reduce the number of generated rules. The method proposed tests each generated rule based on Akaike Information Criteria (AIC) without using conventional thresholds. Experiments with artificial call tracking data show the high performance of the proposed method.

The objective of thinning is to reduce the amount of information in image patterns to the minimum needed for recognition. Thinned image helps the extraction of important features such as end points, junction points, and connections from image patterns. The ultimate goal of parallel algorithms is to minimize the execution time while producing high quality thinned image. Though much research has been performed for parallel thinning algorithms, there has been no systematical approach for comparing the execution speed of parallel thinning algorithms. Several rough comparisons have been done in terms of iteration numbers. But, such comparisons may lead to wrong guides since the time required for iterations varies from one algorithm to the other algorithm. This paper proposes a formal method to analyze the performance of parallel thinning algorithms based on PRAM (Parallel Random Access Machine) model. Besides, the quality of skeletons, robustness to boundary noise sensitivity, and execution speed are considered. Six parallel algorithms, which shows relatively high performance, are selected, and analyzed based on the proposed analysis method. Experiments show that the proposed analysis method is sufficiently accurate to evaluate the performance of parallel thinning algorithms.

Providing various assistances for design modifications on HDL source codes is important for design reuse and quick design cycle in VLSI CAD. Program slicing is a software-engineering technique for analyzing, abstracting, and transforming programs. We show algorithms for extracting/removing behaviors of specified signals in VHDL descriptions. We also describe a VHDL slicing system and show experimental results of efficiently extracting components from VHDL descriptions.

The recently proposed modified PML (MPML) absorbing boundary condition is extended to three dimensions. The performance of the MPML is investigated by FDTD simulation of a typical microstrip line and a rectangular waveguide. The dominant and higher order modes of the microstrip line and the waveguide are excited separately in the computation. In all of the cases of excitation, the reflection properties of the MPML boundaries are examined for the side walls and the end walls, respectively. Various values of the permittivity and permeability of the MPML medium are tested in the computation, and the variation behavior of reflection from the MPML boundaries is examined. The numerical results reveal that by choosing appropriate values of the permittivity and permeability of the MPML, we can realize efficient absorption of both evanescent waves and propagating waves over a wide frequency band.

Hardware software codesign using various hardware and software implementation possibilities requires a cosimulation environment which has both flexibility and efficiency. In this paper, a hardware software cosimulation environment is developed using the backplane approach and optimized synchronization. To seamlessly integrate a new simulator, this paper defines and implements the backplane protocol for communication and synchronization between client simulators. Automatic interface generation facility is also devised for more effective cosimulation environment. To enhance the performance of cosimulation backplane, a series of optimized hardware software synchronization methods are introduced. Efforts are focused on reducing control packets between simulators as well as concurrent execution of simulators without roll-back. The environment is implemented based on Ptolemy and validated with a QAM example run on different configurations. With optimized synchronization method, we have achieved about 7 times speed-up compared with the lock-step synchronization.