A novel method is proposed to calculate the distributed coupling of dual-modes in a circular resonator. New theoretical expressions are devised to accumulate the infinitesimal coupling between orthogonal modes and their validity is justified by the FD-TD analysis and experiments. The distributed coupling concept of a circular disk resonator is applied to a square disk resonator to calculate its resonant frequency. We have fabricated two types of low-profile dual-mode square dielectric disk resonator BPF, using high dielectric constant material (εr = 93) having a dimension of 5 mm 5 mm 1 mm. The filter characteristics are explained by the transmission line circuit model.

The tera-bit order capacity of ultrahigh-speed and wide-band networks will become necessary to provide highly advanced multimedia services. In conventional networks, electronic circuits limit the speed capability of the networks. Consequently, all-optical networks are essential to realize ultrahigh-speed and wide-band communications. In this paper, we propose the configuration of an all-optical code division multiplexing (CDM) switching network based on self-routing principles and the structure of a nonlinear all-optical switching device as one of the key components for the network. We show that the required performances of the optical devices used in the CDM switching fabric are lower than those used in the TDM and illustrate the basic transmission characteristics of the switching device utilizing FD-BPM. To evaluate the multiplexing performance, we demonstrate the maximum number of channels under an error-free condition and the BER characteristics when the Gold sequence is applied as one of the CDM code sets, and show that the network of the sub-tera-bit order capacity is realizable by adopting TDM, WDM and CDM technologies. We also illustrate the packet assembly method suitable for self-routing transmissions and one of network architectures where the proposed switching fabric can be exploited.

Given two terms and their rewriting rules, an unreachability problem proves the non-existence of a reduction sequence from one term to another. This paper formalizes a method for solving unreachability problems by abstraction; i. e. , reducing an original concrete unreachability problem to a simpler abstract unreachability problem to prove the unreachability of the original concrete problem if the abstract unreachability is proved. The class of rewriting systems discussed in this paper is called β rewriting systems. The class of β rewriting systems includes very important systems such as semi-Thue systems and Petri Nets. Abstract rewriting systems are also a subclass of β rewriting systems. A β rewriting system is defined on axiomatically formulated base structures, called β structures, which are used to formalize the concepts of "contexts" and "replacement," which are common to many rewritten objects. Each domain underlying semi-Thue systems, Petri Nets, and other rewriting systems are formalized by a β structure. A concept of homomorphisms from a β structure (a concrete domain) to a β structure (an abstract domain) is introduced. A homomorphism theorem (Theorem1)is established for β rewriting systems, which states that concrete reachability implies abstract reachability. An unreachability theorem (Corollary1) is also proved for β rewriting systems. It is the contraposition of the homomorphism theorem, i. e. , it says that abstract unreachability implies concrete unreachability. The unreachability theorem is used to solve two unreachability problems: a coffee bean puzzle and a checker board puzzle.

In this paper, we discuss the problem of active training data selection for improving the generalization capability of a neural network. We look at the learning problem from a function approximation perspective and formalize it as an inverse problem. Based on this framework, we analytically derive a method of choosing a training data set optimized with respect to the Wiener optimization criterion. The final result uses the apriori correlation information on the original function ensemble to devise an efficient sampling scheme which, when used in conjunction with the learning scheme described here, is shown to result in optimal generalization. This result is substantiated through a simulated example and a learning problem in high dimensional function space.

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.

This paper describes low-power architecture-methodologies for programmable multimedia processors, which will become major functional units in System-On-a-Chip. After brief review on multimedia processing and low-power considerations, recent programmable chips, including MPUs and DSPs, are investigated in terms of low-power implementation. In order to show the difference of the low-power approaches between programmable processors and ASIC processors, a single-chip MPEG-2 encoder is also included as an example of ASIC design.

DC offset causes performance degradation in signal processing systems especially for high-speed applications. A new offset cancellation method that relaxes the requirement for the offset of the circuit components in the differential analog data path to about 10 times larger is introduced. This method moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the final offset cancellation. It eliminates post-production adjustment such as fuse trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibration circuit is implemented in a small silicon space in a high-speed hard disk drive (HDD) channel with 0.25-µm four-layer metal CMOS process. The measured data show this method works effectively in this system.

This paper describes a new reconfigurable processor architecture called REMARC (Reconfigurable Multimedia Array Coprocessor). REMARC is a small array processor that is tightly coupled to a main RISC processor. It consists of a global control unit and 64 16-bit processors called nano processors. REMARC is designed to accelerate multimedia applications, such as video compression, decompression, and image processing. These applications typically use 8-bit or 16-bit data therefore, each nano processor has a 16-bit datapath that is much wider than those of other reconfigurable coprocessors. We have developed a programming environment for REMARC and several realistic application programs, DES encryption, MPEG-2 decoding, and MPEG-2 encoding. REMARC can implement various parallel algorithms which appear in these multimedia applications. For instance, REMARC can implement SIMD type instructions similar to multimedia instruction extensions for motion compensation of the MPEG-2 decoding. Furthermore, the highly pipelined algorithms, like systolic algorithms, which appear in motion estimation of the MPEG-2 encoding can also be implemented efficiently. REMARC achieves speedups ranging from a factor of 2.3 to 21.2 over the base processor which is a single issue processor or 2-issue superscalar processor. We also compare its performance with multimedia instruction extensions. Using more processing resources, REMARC can achieve higher performance than multimedia instruction extensions.

The hybrid electrical/optical multi-chip integration technique for optical modules for optical network system has been developed. Employing the technique, a 44 broadcast-and-select type optical matrix switch module has been realized. The module consists of four sets of silica waveguide 1 : 4 splitters/4 : 1 combiners, four 4-channel arrays of polarization insensitive semiconductor optical amplifiers with spot-size converters as optical gates, printed wiring chips for electrical wiring and single mode fibers for optical signal interface on planar waveguide platform fabricated by atmospheric pressure chemical vapor deposition. All the gates and the wiring chips were mounted precisely onto the platform at once in flip-chip manner by self-align technique using AuSn solder bumps. Coupling loss between the waveguide and the SOA gate was estimated to be 4.5 dB. Averaged fiber-to-fiber signal gain, on-off ratio and polarization dependent loss for each of the signal paths was 7 dB 2 dB, more than 40 dB and 0.5 dB, respectively. High speed 10 Gb/s photonic cell switching as short as 2 nsec has been successfully achieved.

A novel testing-pad placement method has been developed to greatly improve E-beam observability for multi-level wiring LSIs. In the method, testing pads connecting a lower-metal-layer wire with a top-metal-layer electrode are positioned in the design layout, making removal of the insulator unnecessary. The method features i) pad placement in unoccupied areas in mask patterns to avoid increases in chip size, ii) minimized pad size through the use of stacked vias so that the pads can be placed on as many wire nodes as possible, iii) placement as far as possible from the nearby wires to avoid local field effects, and iv) allocation of one testing pad to one circuit node to minimize the number of testing pads. These measures give us a practical pad-placement method, that has little influence on LSI design. It was shown that the proposed method yielded a dramatic improvement of observability from 13-33% to 88-99% in actual layouts of 0.25-µm ASICs with 20k, 120k, and 390k gates. It was also found that local field effects from nearby wires are negligible for almost all the testing pads. This approach will enable the use of E-beam testing on LSIs made with 0.25-µm technology and the even more sophisticated process technologies to come.

We propose and demonstrate for the first time in our knowledge, an optical switch circuit architecture furnishing with the "Bridge and Switch" function, conforming to ITUT-T Recommendation G. 841 Annex A for optical Add-Drop Multiplexers (ADMs) in WDM four-fiber ring networks. This function enables optical ADMs to revert automatically from the switching state to their idle state just after the recovery of failure, that is indispensable for the extra traffic accommodation to enhance efficiency of the network operation. oWe have developed the optical ADM nodes employing the proposed optical switch circuit for each wavelength, arrayed-waveguide gratings (AWGs) and Er-doped fiber amplifiers. In the demonstration, transmission characteristics of the cascaded optical ADM nodes without regenerative repeaters have been verified at first. We have confirmed the ring protection and the automatic protection switching (APS) sequence which includes the automatic reversion in the optical ADM nodes with proposed optical switch circuits.

A 116 arrayed waveguide grating multiplexer operating around 1550 nm has been realized using newly synthesized fluorinated poly(arylene ethers). The channel spacing is 0.8 nm (100 GHz). The insertion loss of the multiplexer is 17-20 dB and the cross talk is less than -15 dB. The propagation loss of a rib waveguide is less than 0.5 dB/cm at 1550 nm.

Recent progress in the optical transmission technology makes an ATM passive optical network (APON) a good candidate for access networks. APON based on tree topology requires efficient medium access control (MAC) to multiplex upstream data flows efficiently while not disturbing the original pattern. In this paper, we proposed a Window-based permit distribution scheme for the MAC protocol of APON. It derives the rate of generated cell during one spacing window by the unit called time segment, and spaces permits not to cluster the cells in upstream transmission. The purpose of the proposed scheme is to make the permit arrival rate close to the cell arrival rate, so, reduces the CDV even if under the various kinds of bursty traffic. In addition, the proposed scheme does not require the additional MAC overhead for cell arrival timing information. The result of simulation shows that the performance of proposed protocol is better than current protocols in terms of transfer delay and 1-point CDV.

Predicate Circumscription is a fundamental formalization of common sense reasoning. In this paper, we study a new approximation formula of it. In our previous works, we investigated Lifschitz's pointwise circumscription and its generalization, which functions as a finite approximation to predicate circumscription in the first-order framework. In this paper, at first, we study the ability of the generalized pointwise circumscription more closely, and give a simple example which shows that it cannot be complete even when a minimized predicate has only finite extension on the minimal models. Next, we introduce a new approximation formula, called finite constructive circumscription, in order to overcome that limitation. Finally, we compare expressive power of the two approximation methods with of predicate circumscription schema, and propose a open problem that should be solved to clarify that the completeness of predicate circumscription schema with respect to minimal model semantics.

Operation of fiber-grating semiconductor laser (FGL) has been stabilized by using the semiconductor optical amplifier which has a simple slant-waveguide structure. The emission wavelength, which depends on a temperature, shows hysteresis. Employing the directly modulated FGL at 2.5 Gb/s, transmission over 400 km in standard optical fiber has been successfully achieved.

Noise greatly degrades the image quality and performance of image compression algorithms. This paper presents an approach for the representation and compression of noisy synthetic images. A new concept region-based prediction (RBP) model is first introduced, and then the RBP model is utilized on noisy images. In the conventional predictive coding techniques, the context for prediction is always composed of individual pixels surrounding the pixel to be processed. The RBP model uses regions instead of individual pixels as the context for prediction. An algorithm for the implementation of RBP is proposed and applied to noisy synthetic images in our experiments. Using RBP to find the residual data and encoding them, we achieve a bit rate of 1.10 bits/pixel for the noisy synthetic image. The decompressed image achieves a peak SNR of 42.59 dB. Compared with a peak SNR of 41.01 dB for the noisy synthetic image, the quality of the decompressed synthetic image is improved by 1.58 dB in the MSE sense. In contrast to our proposed compression algorithm with its improvement in image quality, conventional coding methods can compress image data only at the expense of lower image quality. At the same bit rate, the image compression standard JPEG provides a peak SNR of 33.17 dB for the noisy synthetic image, and the conventional median filter with a 33 window provides a peak SNR of 25.89 dB.

Design and evaluation of a high-performance switch architecture for free-space photonic switching systems is described. The switch is constructed of 22 switching elements and employs special multistage interconnection patterns. The connection setup algorithm and the control procedure at the switching elements are based on a "rerouting algorithm." Performance analysis shows that the blocking probability of the switch is easily controlled by increasing the number of switching stages. Example implementations of this switch are shown in which birefringent plates, polarization controllers, etc. are used.

State of the arts on guided-wave optical switch arrays are reviewed. In this paper, electro-optic Ti:LiNbO3 devices are mainly described in comparison with crosspoint switch element structures and switch array architectures. Packaging technologies and stability problems are discussed for practical system applications. Recent development on other materials such as semiconductor waveguides, thermo-optic glass/polymer waveguides are also reviewed briefly.

Template learning has potential application in several areas of Cellular Neural Network research, including texture recognition, pattern detection and so on. In this letter, a recently-developed algorithm called Adaptive Simulated Annealing is investigated for learning CNN templates, as a superior alternative to the Genetic Algorithm.

A packet-based leaky-bucket algorithm functions like the early packet discard (EPD), and accepts a newly arriving packet if the probability that all the cells of the packet are accepted is high. We derive some performance characteristics of the cell and packet arrival processes that are accepted by the leaky-bucket algorithm. From these analyses, a method to determine the values of the parameters of the leaky-bucket algorithm and certain relations between this leaky-bucket algorithm and the generic cell rate algorithm (GCRA) are obtained.