The equivalence between Aperture Field Integration Method (AFIM) and Physical Optical (PO) is discussed for polyhedron surfaces in this paper. The necessary conditions for the equivalence are summarized which demand complete equivalent surface currents and complete apertures. The importance of the exact expressions for both incident and reflected fields in constructing equivalent surface currents is emphasized and demonstrated numerically. The fields from reflected components on additional surface which lies on the Geometrical Optics (GO) reflection boundary are evaluated asymptotically. The analytical expression enhances the computational efficiency of the complete AFIM. The equivalent edge currents (EECs) for AFIM (AFIMEECs) are used to extract the mechanism of this equivalence between AFIM and PO.

This paper presents a new compound constructive algorithm of neural networks whereby the fuzzy logic technique is explored as an efficient learning algorithm to implement an optimal network construction from an initial simple 3-layer network while the genetic algorithm is used to help design an improved network by evolutions. Numerical simulations on artificial life demonstrate that compared with the existing network design algorithms such as the constructive algorithms, the pruning algorithms and the fixed, static architecture algorithm, the present algorithm, called FuzGa, is efficient in both time complexity and network performance. The improved time complexity comes from the sufficiently small 3 layer design of neural networks and the genetic algorithm adopted partly because the relatively small number of layers facilitates an utilization of an efficient steepest descent method in narrowing down the solution space of fuzzy logic and partly because trappings into local minima can be avoided by genetic algorithm, contributing to considerable saving in time in the processing of network learning and connection. Compared with 54. 8 minutes of MLPs with 65 hidden neurons, 63. 1 minutes of FlexNet or 96. 0 minutes of Pruning, our simulation results on artificial life show that the CPU time of the present method reaching the target fitness value of 100 food elements eaten for the present FuzGa has improved to 42. 3 minutes by SUN's SPARCstation-10 of SuperSPARC 40 MHz machine for example. The role of hidden neurons is elucidated in improving the performance level of the neural networks of the various schemes developed for artificial life applications. The effect of population size on the performance level of the present FuzGa is also elucidated.

In the spatial network method (SNM) for the vector potential, both the current continuity law including polarization vector and the conservation law of generalized momentum including vector potential field can introduce simpler expressions for dispersive property than that by the electromagnetic field variables. But for the anisotropic medium conditions, the conventional expanded node expression has some difficulties in treating the coupling mechanism among field variables. On the other hand, in the condensed node expression, in which all field components exist at each node, every connections among field components can be simply formulated. In this paper, after proposing the condensed node spatial network method for the vector potential, the advantage of the method such as performing the simplified formulation by utilization of both the vector potential and the condensed node expressions is presented for the magnetized plasma which has the gyro-anisotropy. The validity of the computation is shown by some examples such as Faraday rotation.

This paper shows an analysis of electromagnetic scattering from an open-ended rectangular cylinder for a plane wave incidence. The internal region is separated into two areas by additional plates to investigate the cavity resonance in detail. The applied numerical technique is the point matching method taking account of the edge condition. As numerical examples, the radar cross section is presented for E - polarized case and H - polarized case. Physical meanings of the computational results are discussed with a view to the contribution of the iris.

A high performance voltage down converter (VDC) is proposed in this paper. The proposed VDC can automatically control the driving current in seven phases to reduce the fluctuation of output voltage in VDC. By using above new flexible control technology of driving current, the fluctuation of output voltage can be suppressed to less than 10% and the average consuming current of VDC can be suppressed to 34 µA, even if the operation frequency is 200 MHz at the average driving current 100 mA. Therefore, the proposed VDC can operate with large driving current, low-power consumption and good response at the same time. Above all, this technology is very suitable for high perform ULSIs which require large load current, very low-power and high speed operation.

This paper discusses a method to evaluate mutual couplings of cavity-backed slot antennas using the FDTD technique. The antenna fed by the short-ended probe is considered, which is investigated as an element of the power transmission antenna, Spacetenna, for the solar power satellite SPS2000. It is found from the FDTD computation on E-plane two- and four-element array antennas that the size of the problem space should be larger for the evaluation of the mutual coupling than for the estimation of the input impedance. Since enlarging the size of the problem space requires a large amount of computer storage, it is not practical for computer simulations. In order to carry out accurate estimations of the mutual coupling with relatively small amount of computer memory, the problem space is extended only in the broadside of the array antenna and in the other directions there are ten cells between the antenna surface and the outer boundary. Computer simulations demonstrate that there are no differences between the results of the proposed problem space geometry and the problem space extended in each direction of the axis coordinate by the same number of cells. Furthermore comparisons of computed and experimental results demonstrate the effectiveness of the approach after discussing how large the size of the problem space is required to estimate the mutual coupling.

In this paper, we present an analysis of the microstrip lines whose strip conductors are of various cross-sections, such as rectangular cross-section, triangle cross-section, and half-cycle cross-section. The method employed is the boundary integral equation method (BIEM). Numerical results for these microstrip lines demonstrate various shape effects of the strip conductor on the characteristics of lines. The processing technique on the convergence of the Green's function is also described.

MOSFETs with sub-0.1 µm gate length were fabricated, and their low temperature operation was investigated. The drain current for drain voltage of 2 V increased monotonously as temperature was lowered to 15 K without an influence of the freeze-out effect. Moreover, the increase in the drain current was enhanced by the gate length reduction. The hot-carrier effect at low temperature was also investigated. Impact-ionization decreased as temperature was lowered under the condition of drain voltage 2 V. The decreasing ratio was enhanced as gate length became shorter. We consider this phenomenon is attributed to the non-steady-stationary effect. As a result, device degradation by DC stressing was reduced at 77 K in comparison with room temperature. In the case of 0.1 µm MOSFET, drain current was not degraded in condition of DC stress with gate- and drain-voltage was 1.5 V.

A decision-directed carrier phase recovery scheme for high-speed satellite communications is proposed. Since the estimation is performed in complex domain from the baseband signal, the scheme has fast acquisition performance, unlike the conventional PLL. This merit makes it applicable for various wireless systems such as wireless local area networks (LANs), wireless asynchronous transfer modes (ATMs) and local multipoint distribution systems (LMDSs) that need high-speed burst signal communications. Also, this scheme can be implemented easily because low pass filters (LPFs) are utilized in filtering the estimates in order to suppress the noise within the carrier recovery loop. Moreover it does not require any divider or voltage-controlled oscillator (VCO). The performance is analyzed through analytical methods and simulation.

In this paper, we propose a test methodology for core-based system LSIs. Our test methodology aims to decrease testing time for core-based system LSIs. In our method, every core is supplied with several sets of test vectors. Every set of test vectors guarantees sufficient fault coverage. Each set of test vectors consists of two parts. One is based on built-in self-test (BIST) and the other is based on external testing. These sets of test vectors are designed to have different ratio of BIST to external testing each other for every core. We can minimize testing time for core-based system LSIs by selecting from the given sets of test vectors for each core. The main contributions of this paper are summarized as follows. (i) BIST is efficiently combined with external testing to relax the limitation of the external primary inputs and outputs. (ii) External testing for one of cores and BISTs for the others are performed in parallel to reduce the total testing time. (iii) The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal set of test vectors from given sets of test vectors for each core.

In this paper, we will discuss circuit minimization techniques based on the multiple output capability of FPGA blocks. Since previous methods only consider two independent output functions, we will discuss a more complicated case when the two functions are mutually related. We also discuss a method to maximize flexibility of a specified cell output in the given FPGA block. If a set of possible functions for a cell which will not change the FPGA output function is large, we call that the flexibility of this cell is high. The concept of Sets of Pairs of Functions to be Distinguished (SPFDs) introduced by Yamashita et al. is a powerful tool to minimize a given FPGA circuits. In this paper, an extension of the concept, Priority based SPFDs (PSPFDs) is introduced to maximize the flexibility of output functions realized by such internal cells. By using PSPFDs for our new method, we can utilize the multiple output capability very well. Combination with the previous methods with PSPFDs is also shown to be important. We have implemented these methods and applied them to MCNC benchmarks mapped into 5-variable function blocks. To make a comparison with other methods, we have implemented methods using well-known merging algorithms utilizing the same multiple output capability. Experimental results show that our methods can reduce the number of blocks in the initial circuits by 40% on average. This reduction ratio is 16% higher than that of previous methods.

Providing various assistances for design modifications on HDL source codes is important for design reuse and quick design cycle in VLSI CAD. Program slicing is a software-engineering technique for analyzing, abstracting, and transforming programs. We show algorithms for extracting/removing behaviors of specified signals in VHDL descriptions. We also describe a VHDL slicing system and show experimental results of efficiently extracting components from VHDL descriptions.

Hardware software codesign using various hardware and software implementation possibilities requires a cosimulation environment which has both flexibility and efficiency. In this paper, a hardware software cosimulation environment is developed using the backplane approach and optimized synchronization. To seamlessly integrate a new simulator, this paper defines and implements the backplane protocol for communication and synchronization between client simulators. Automatic interface generation facility is also devised for more effective cosimulation environment. To enhance the performance of cosimulation backplane, a series of optimized hardware software synchronization methods are introduced. Efforts are focused on reducing control packets between simulators as well as concurrent execution of simulators without roll-back. The environment is implemented based on Ptolemy and validated with a QAM example run on different configurations. With optimized synchronization method, we have achieved about 7 times speed-up compared with the lock-step synchronization.

The project of interconnecting CATV in Hyogo Prefecture, Japan has started since March, 1998. In this project, there are three CATV companies in Hanshin area; Kobe, Nishinomiya and Amagasaki. An ATM switch is equipped in each company and these CATVs are connected serially in the above order. Each company provides the video service to the rest of companies using the MPEG2 over ATM. Each MPEG2 stream is sent to the other two CATV companies according to the function of multicast implemented in ATM switch. In the coverage of each CATV, subscribers utilize Internet connection using cable modems as well as standard CATV broadcasting service. In this paper, we present the outline of the research project in Hyogo Prefecture, Japan, and examine the jitter processes of MPEG streams of the testbed network by the simulation. In our testbed network, cells with two types of requirement for QoS are multiplexed; cells for MPEG2 which require the real-time transmission and those for Internet packets which are much more sensitive for the cell loss ratio. We investigate the jitter processes under some scenarios and show how the jitter process is affected by the Internet traffic and the other cell streams of MPEG2. Furthermore, we study the effect of the number of ATM switches on the jitter process when more CATV networks are added serially.

Call tracking data contains a calling address, called address, service type, and other useful attributes to predict a customer's calling activity. Call tracking data is becoming a target of data mining for telecommunication carriers. Conventional data-mining programs control the number of association rules found with two types of thresholds (minimum confidence and minimum support), however, often they generate too many association rules because of the wide variety of patterns found in call tracking data. This paper proposes a new method to reduce the number of generated rules. The method proposed tests each generated rule based on Akaike Information Criteria (AIC) without using conventional thresholds. Experiments with artificial call tracking data show the high performance of the proposed method.

In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are 6 kHz of carrier frequency offset, 110 ppm of symbol rate offset, and -82 dBc carrier phase-jitter at 10 kHz away from the nominal carrier frequency.

This paper implements some new techniques to analyze the light beam scattering from a magneto-optical (MO) disk using the three-dimensional finite-difference time-domain (FDTD) method. The anisotropic FDTD update equations are implemented to calculate the propagation of a coherent monochromatic light in the MO material. An anisotropic absorbing boundary condition based on Berenger's perfectly matched layer (PML) concept is also developed. The Gaussian incident light beam is introduced into FDTD computation region exactly by using equivalent electric and magnetic currents. The scattering pattern of light beam from the MO disk is computed and in part compared with that obtained by using the boundary element method. The scattering patterns by the circular recording bit of different radius are calculated to indicate the optimum radius of the recording bit.

In this paper, we describe a routing method for path on SDH Network with digital cross-connect control, which is implemented in an automated path provisioning function. Excessive concentration of assigned time slots at particular links results in longer restoration time, which is needed to switch or reroute paths on failure link. We propose an optimization method to provision the shortest route considering deconcentration of time slots assigned on each link. After defining LP-based formulation for path routing, we carried out computer simulation study for restoration performance on sample networks, assuming each restoration process for paths on failure link is executed one after another. Mean restoration time by our proposed method has reduced to a great extent compared to a basic routing method. It has been proven that the proposed method can realize effective use of resources and faster restoration time, and can be utilized in commercial systems.

The explosive increase of traffic in computer communications is a clear sign that we have entered the multimedia information age. To cope with this ever increasing need, economical optical access networks that support burst traffic such as in the Internet are expected to be developed. The ATM-PON is considered to be a promising candidate for such a network, and vigorous efforts in this direction are being promoted worldwide. This paper focuses on accommodating burst traffic in the ATM-PON. In order to do this, a mechanism to transport bandwidth requests from the ONU to the OLT and an algorithm to support dynamic bandwidth allocations based on ONU requests are needed. We have performed a comparative study on bandwidth request methods and bandwidth allocation algorithms, including bandwidth request dependence on time interval and correlation and/or impact between system design parameters. The results of computer simulations are useful in determining how to accommodate burst traffic efficiently in the ATM-PON.

This paper reports on an Intelligent CASE tool, applicable in a structured programming phase, or from detailed design to coding. This is automation of the bottom level in the hierarchical design process of detailed design and coding, where the largest man-hours are consumed. The main idea is that human designers use a CASE tool for the initial design of a software system, and the design knowledge is automatically acquired from the structured charts and stored in the knowledge base. The acquired design knowledge may be reused in designs. By reusing it, a similar software system may be designed automatically. It has been shown that knowledge acquired in this way has a Logarithmic Learning Effect. Based on this, a quantitative evaluation of productivity is made. By accumulating design experiences (e. g. 10 times), more than 80% of the detailing designs are performed automatically, and productivity increases by up to 4 times. This tool features universality, an essentially zero start-up cost for automatic design, and a substantial increase in software productivity after enough experiences have been accumulated. This paper proposes a new basic idea and its implementation, a quantitative evaluation applying techniques from Industrial Engineering, which proves the effectiveness of the proposed system.