Spot-size-converter integrated semiconductor optical amplifiers have been developed as gate elements for optical switch matrices. An S-shape waveguide has been introduced to prevent re-coupling of unguided light to the output fiber. An angled-facet structure effectively suppressed light reflection at the end facets. Consequently, a high extinction ratio of 70 dB and a high fiber-to-fiber gain of 20 dB were achieved. Sufficient optical coupling characteristics to a flat-ended single-mode fiber with a coupling loss of 3.5 dB were also demonstrated.

To enhance the extinction ratio (ER) of NRZ-to-inverted-RZ converter based on cross-gain compression of a semiconductor optical amplifier (SOA), a modified terahertz optical asymmetric demultiplexer (TOAD) is cascaded. ER is improved from 1.6-6.7 dB to 5.4-14.5 dB, depending on the intensity of input optical NRZ signal. The proposed NRZ-to-inverted-RZ converter enhances and regulates ER to a high value (14.5 dB) for very wide optical NRZ signal intensity range.

Operation of fiber-grating semiconductor laser (FGL) has been stabilized by using the semiconductor optical amplifier which has a simple slant-waveguide structure. The emission wavelength, which depends on a temperature, shows hysteresis. Employing the directly modulated FGL at 2.5 Gb/s, transmission over 400 km in standard optical fiber has been successfully achieved.

This paper proposesd a non-blocking multi-stage ATM switch based on a hierarchical-cell-resequencing (HCR) mechanism and high-speed WDM interconnection and reports on its feasibility study. In a multi-stage ATM switch, cell-based routing is effective to make the switch non-blocking, because all traffic is randomly distributed over intermediate switching stages. But due to the multi-path conditions, cells may arrive out of sequence at the output of the switching fabric. Therefore, resequencing must be performed either at each output of the final switching stage or at the output of each switching stage. The basic HCR switch performs cell resequencing in a hierarchical manner when switching cells from an input-lines to a output-line. As a result, the cell sequence in each output of the basic HCR switch is recovered. A multi-stage HCR switch is constructed by interconnecting the input-lines and output-lines of these basic HCR switches in a hierarchical manner. Therefore, the cell sequence in each final output of the switching fabric is conserved in a hierarchical manner. In this way, cell-based routing becomes possible and a multi-stage ATM switch with the HCR mechanism can achieve 100% throughput without any internal speed-up techniques. Because a large-capacity multi-stage HCR switch needs a huge number of high-speed signal interconnections, a breakthrough in compact optical interconnection technology is required. Therefore, this paper proposes a WDM interconnection system with an optical router arrayed waveguide filter (AWGF) that interconnects high-speed switch elements effectively and reports its feasibility study. In this architecture, each switch element is addressed by a unique wavelength. As a result, a switch in a previous stage can transmit a cell to any switch in the next stage by only selecting its cell transmission wavelength. To make this system feasible, we developed a wide-channel-spacing optical router AWGF and compact 10-Gbit/s optical transmitter and receiver modules with a compact high-power electroabsorption distributed feedback (EA-DFB) laser and a new bit decision circuit. Using these modules, we confirmed stable operation of the WDM interconnection. This switch architecture and WDM interconnection system should enable the development of high-speed ATM switching systems that can achieve throughput of over 1 Tbit/s.

Since the inception of optical networking, a goal has been to create an all-optical network. The rapid breakthrough for WDM in point to point links has brought this prospect considerably closer, however, at the same time, questions regarding the scalability of the all-optical network remain. In this paper, we review our recent research in this area, partly performed within the European Union project METON (METropolitan Optical Network), and discuss the all-optical approach and different optoelectronic alternatives, mainly of the 2R (reamplify and reshape) type.

Lots of self-tuning control schemes have been proposed for tuning the parameters of control systems. Among them, pole-assignment schemes have been widely used for tuning the parameters of control systems with unknown time delays. They are usually classified into two methods, the implicit and the explicit methods according to how to identify the parameters. The latter has an advantage to design a control scheme by taking account of the stability margin and control performance. However, it involves a considerably computational burden to solve a Diophantine equation. A simple scheme is proposed in this paper, which can construct a multivariable self-tuning pole-assignment control system, while taking account of the stability margin and control performance without solving a Diophantine equation.

DC offset causes performance degradation in signal processing systems especially for high-speed applications. A new offset cancellation method that relaxes the requirement for the offset of the circuit components in the differential analog data path to about 10 times larger is introduced. This method moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the final offset cancellation. It eliminates post-production adjustment such as fuse trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibration circuit is implemented in a small silicon space in a high-speed hard disk drive (HDD) channel with 0.25-µm four-layer metal CMOS process. The measured data show this method works effectively in this system.

Layout has strong influence on matching properties of a circuit. Current matching models, which characterize both local random non-uniformities and global systematic non-uniformities stochastically, are not adequate for the matching analysis taking the effect of layout realization into account. In order to consider topological information of layout into matching analysis, we propose a matching model which treats the random and systematic components separately. Also, we characterize the micro-loading effect, which modulates fabricated line-width according to the local density of layout patterns, into matching analysis. With these two techniques, we can perform matching analysis of CMOS circuits taking layout information into account.

Multi-input floating gate differential amplifier (FGDA) is proposed which can perform any convolution operation with differential structure and feedback loop. All operations are in the voltage mode. Only one terminal is required for the negative feedback which can suppress distortions due to mismatches of active elements. Possible applications include intelligent image sensor, where fully parallel DCT operation can be performed. A prototype chip is fabricated which is functional. A preliminary test result is reported.

This paper proposes a method to transform a CORDIC ARMA lattice filter, which is originally realized for signal analysis, into a signal synthesis lattice filter (CORDIC ARMA lattice synthesis filter). In order to perform such a transformation and then obtain the CORDIC ARMA lattice synthesis filter, we must implement the followings with CORDIC: (1) the structure of the altered lattice filter; and (2) an angle calculation module. However, we cannot achieve such an implementation as an extension of the CORDIC ARMA lattice filter algorithm. Therefore, this paper proposes CORDIC implementation schemes for both the structure and module, and then we realize the CORDIC ARMA lattice synthesis filter. By using CORDIC processors, the elementary sections of the CORDIC ARMA lattice synthesis filter are efficiently implemented without any multipliers. Since the obtained signal synthesis lattice filter consists of dedicated CORDIC processors, it keeps the advantage of the CORDIC ARMA lattice filter, that is a simple structure.

Digital Signal Processors with complex arithmetic capability (DSP-C) are useful for various applications. In this paper, we propose a method for the effective implementation of specific circuits with real coefficients on DSP-C. DSP-C has special hardware such as a complex multiplier so that a complex calculation can be performed with only one instruction. First, we show that nodes with two real coefficient input branches can be implemented by complex multiplications. We apply this implementation to 2D circuits and transversal circuits with real coefficients. Next, we introduce a new computational mode (Advanced mode) and a new multiplier into PSI, a kind of DSP-C which has been proposed already, in order to process the circuits effectively. The effectiveness of the proposed method is shown by simulation in the last part.

State of the arts on guided-wave optical switch arrays are reviewed. In this paper, electro-optic Ti:LiNbO3 devices are mainly described in comparison with crosspoint switch element structures and switch array architectures. Packaging technologies and stability problems are discussed for practical system applications. Recent development on other materials such as semiconductor waveguides, thermo-optic glass/polymer waveguides are also reviewed briefly.

A pipelined architecture is proposed for the normalized least mean square (NLMS) adaptive digital filter (ADF). Pipelined implementation of the NLMS has not yet been proposed. The proposed architecture is the first attempt to implement the NLMS ADF in the pipelined fashion. The architecture is based on an equivalent expression of the NLMS derived in this study. It is shown that the proposed architecture achieves a constant and a short critical path without producing output latency. In addition, it retains the advantage of the NLMS, i. e. , that the step size that assures the convergence is determined automatically. Computer simulation results that confirm that the proposed architecture achieves convergence characteristics identical to those of the NLMS.

Wavelength division multiplex (WDM) photonic networks are expected as the key for the global communication infrastructure. Recent increase of communication demands require large-scale highly-dense WDM systems, which results in severe requirements for optical cross-connect systems, such as cross-talk specification. In this paper, we propose a new optical path cross-connect system (OPXC) using matrix-WDM scheme, which makes it possible to reduce cross-talk requirements of WDM filters and to construct OPXC in modular structures. The matrix-WDM scheme is a concept of two-layered optical paths, which provides wavelength group managements in the fiber dispersion equalization and EDFA gain equalization.

In this letter, a new scheme of designing two-level minimum mean square error quantizer for image coding is proposed. Genetic algorithm is applied to achieve this goal. Comparisons of results with various methods have verified, the proposed method can reach nearly optimal quantization with only less iterations.

We experimentally demonstrate the ultrafast and high-repetition capabilities of a polarization-discriminating symmetric Mach-Zehnder (PD-SMZ) all-optical switch. This switch, as well as an original symmetric Mach-Zehnder (SMZ) all-optical switch, is based on a highly efficient but slowly relaxing band-filling effect that is resonantly excited in a passive InGaAsP bulk waveguide. By using a mechanism that cancels out the effect of the slow relaxation, ultrafast switching is attained. We achieve a switching time of 200 fs and demultiplexing of 1.5 Tbps, showing the applicability of the SMZ or PD-SMZ all-optical switches to optical demultiplexing of well over 1 Tbps for the first time. High-repetition capability, which is another important issue apart from the switching speed, is also verified by using control pulses at a repetition rate of 10.5 GHz. We also discuss the use of nonlinearity in a semiconductor optical amplifier to further reduce the control-pulse energy.

We propose and demonstrate for the first time in our knowledge, an optical switch circuit architecture furnishing with the "Bridge and Switch" function, conforming to ITUT-T Recommendation G. 841 Annex A for optical Add-Drop Multiplexers (ADMs) in WDM four-fiber ring networks. This function enables optical ADMs to revert automatically from the switching state to their idle state just after the recovery of failure, that is indispensable for the extra traffic accommodation to enhance efficiency of the network operation. oWe have developed the optical ADM nodes employing the proposed optical switch circuit for each wavelength, arrayed-waveguide gratings (AWGs) and Er-doped fiber amplifiers. In the demonstration, transmission characteristics of the cascaded optical ADM nodes without regenerative repeaters have been verified at first. We have confirmed the ring protection and the automatic protection switching (APS) sequence which includes the automatic reversion in the optical ADM nodes with proposed optical switch circuits.

The application of photonic technologies to packet switching offers the potential of very large switch capacity in the terabit per second range. The merging of packet switching with photonic technologies opens up the possibility of packet switching in transparent photonic media, in which packets remain in optical form without undergoing optoelectronic conversion. This paper reviews recent work on photonic packet switching. Different approaches to photonic packet switching and key design issues are discussed.

Optoelectronic hybrid integration is a promising technology for realizing the optical components needed in optical transmission, switching, and interconnection systems that use wavelength division multiplexing (WDM) and time division multiplexing (TDM). We have already developed versatile optical hybrid integrated modules using a silica-based planar lightwave circuit (PLC) platform. However, these modules consist solely of the optoelectronic semiconductor devices such as laser diodes (LDs) and photo diodes (PDs) and monolithic optoelectronic integrated circuits (OEICs). To carry out high-speed and versatile electric signal processing functions in future network systems, it is necessary to install semiconductor electrical integrated circuits (ICs) on a PLC platform. In this paper, we describe novel technologies for high-speed PLC platforms which make it possible to assemble both ICs and optoelectronic devices. Using these technologies, we fabricated a two-channel hybrid integrated optical transmitter module which is hybrid integrated with an LD array chip and an LD driver IC. On this PLC platform, we use microstrip lines (MSLs) to drive the LD driver IC. We also considered the effect of heat interference on the LD array chip caused by the LD driver IC when designing the layout of the chip assembly region. The LD array chip and the LD driver IC were flip-chip bonded with solder bumps of a different material to avoid any deterioration in the coupling efficiency of the LD array chip. The optical transmitter module we fabricated operated successfully at 9 Gbit/s non-return-zero (NRZ) signal. This approach using a PLC platform for the hybrid integration of an LD array chip and an LD driver IC will carry forward the development of high-speed optoelectronic modules with both optical and electrical signal processing functions.

Recent work in the area of ultrafast optical time-division multiplexed (OTDM) networking at MIT Lincoln Laboratory is presented. A scalable helical local area network or HLAN architecture, presented elsewhere as an architecture well-suited to ultrafast OTDM LANs and MANs, is considered in the context of wide area networking. Two issues arise in scaling HLAN to the wide area. The first is protocol extension, and the second is supporting the required bandwidth on the long-haul links. In this paper we discuss these challenges and describe progress made in both architecture and technologies required for scaling HLAN to the wide area.