Spot-size-converter integrated semiconductor optical amplifiers have been developed as gate elements for optical switch matrices. An S-shape waveguide has been introduced to prevent re-coupling of unguided light to the output fiber. An angled-facet structure effectively suppressed light reflection at the end facets. Consequently, a high extinction ratio of 70 dB and a high fiber-to-fiber gain of 20 dB were achieved. Sufficient optical coupling characteristics to a flat-ended single-mode fiber with a coupling loss of 3.5 dB were also demonstrated.

This paper proposes a fast synchronization scheme with a short preamble signal for high data rate wireless LAN systems using orthogonal frequency division multiplexing (OFDM). The proposed OFDM burst format for fast synchronization and the demodulator for the proposed OFDM burst format are described. The demodulator, which offers automatic frequency control and symbol timing detection, enables us to shorten the preamble length to one quarter that of a conventional one. Computer simulation results show that the degradation in required Eb/N0 due to the synchronization scheme is less than 1 dB in a selective Rayleigh fading channel.

To enhance the extinction ratio (ER) of NRZ-to-inverted-RZ converter based on cross-gain compression of a semiconductor optical amplifier (SOA), a modified terahertz optical asymmetric demultiplexer (TOAD) is cascaded. ER is improved from 1.6-6.7 dB to 5.4-14.5 dB, depending on the intensity of input optical NRZ signal. The proposed NRZ-to-inverted-RZ converter enhances and regulates ER to a high value (14.5 dB) for very wide optical NRZ signal intensity range.

This paper proposesd a non-blocking multi-stage ATM switch based on a hierarchical-cell-resequencing (HCR) mechanism and high-speed WDM interconnection and reports on its feasibility study. In a multi-stage ATM switch, cell-based routing is effective to make the switch non-blocking, because all traffic is randomly distributed over intermediate switching stages. But due to the multi-path conditions, cells may arrive out of sequence at the output of the switching fabric. Therefore, resequencing must be performed either at each output of the final switching stage or at the output of each switching stage. The basic HCR switch performs cell resequencing in a hierarchical manner when switching cells from an input-lines to a output-line. As a result, the cell sequence in each output of the basic HCR switch is recovered. A multi-stage HCR switch is constructed by interconnecting the input-lines and output-lines of these basic HCR switches in a hierarchical manner. Therefore, the cell sequence in each final output of the switching fabric is conserved in a hierarchical manner. In this way, cell-based routing becomes possible and a multi-stage ATM switch with the HCR mechanism can achieve 100% throughput without any internal speed-up techniques. Because a large-capacity multi-stage HCR switch needs a huge number of high-speed signal interconnections, a breakthrough in compact optical interconnection technology is required. Therefore, this paper proposes a WDM interconnection system with an optical router arrayed waveguide filter (AWGF) that interconnects high-speed switch elements effectively and reports its feasibility study. In this architecture, each switch element is addressed by a unique wavelength. As a result, a switch in a previous stage can transmit a cell to any switch in the next stage by only selecting its cell transmission wavelength. To make this system feasible, we developed a wide-channel-spacing optical router AWGF and compact 10-Gbit/s optical transmitter and receiver modules with a compact high-power electroabsorption distributed feedback (EA-DFB) laser and a new bit decision circuit. Using these modules, we confirmed stable operation of the WDM interconnection. This switch architecture and WDM interconnection system should enable the development of high-speed ATM switching systems that can achieve throughput of over 1 Tbit/s.

We propose novel all-optical functional devices using waveguide X-junctions with localized third order optical nonlinearity, where one branch is made from a Kerr-like nonlinear material and the rest are made from linear ones. All-optical switching operations can be obtained because of bistable like nonlinear dispersion characteristics in linear and nonlinear coupled guided-wave systems. The performances of the devices are analyzed by the Beam Propagation Method (BPM) modified for nonlinear waveguides combined with the nonlinear normal mode analysis. The methods to construct the waveguides with localized nonlinearity are also discussed by utilizing the technologies for the selective control of a band-gap energy of semiconductor Multi Quantum Well (MQW) structures and the performances of the designed devices are presented.

We propose and demonstrate for the first time in our knowledge, an optical switch circuit architecture furnishing with the "Bridge and Switch" function, conforming to ITUT-T Recommendation G. 841 Annex A for optical Add-Drop Multiplexers (ADMs) in WDM four-fiber ring networks. This function enables optical ADMs to revert automatically from the switching state to their idle state just after the recovery of failure, that is indispensable for the extra traffic accommodation to enhance efficiency of the network operation. We have developed the optical ADM nodes employing the proposed optical switch circuit for each wavelength, arrayed-waveguide gratings (AWGs) and Er-doped fiber amplifiers. In the demonstration, transmission characteristics of the cascaded optical ADM nodes without regenerative repeaters have been verified at first. We have confirmed the ring protection and the automatic protection switching (APS) sequence which includes the automatic reversion in the optical ADM nodes with proposed optical switch circuits.

The application of photonic technologies to packet switching offers the potential of very large switch capacity in the terabit per second range. The merging of packet switching with photonic technologies opens up the possibility of packet switching in transparent photonic media, in which packets remain in optical form without undergoing optoelectronic conversion. This paper reviews recent work on photonic packet switching. Different approaches to photonic packet switching and key design issues are discussed.

A large scale optical switch array based on guided-wave technology using banyan network architecture is demonstrated. Banyan network architecture is the simplest NN network connecting a input port to all the output ports. A banyan network optical switch array serves as a base for constructing many classes of switch networks, as we propose in this report. We fabricated a 3232 switch and measured its characteristics. Drive voltage was about 12 V and extinction ratio was 18 dB, and the average insertion loss was 18 dB. Preliminary experiments were conducted on a 6464 device. The use of proton exchanged waveguides makes a 10 mm radius of curvature feasible.

By adopting a network architecture in which not only a calling but also a called terminal can select a wavelength, a novel WDM network becomes possible. This we call Wavelength Assignment Photonic Network (WAPN). In this network wavelengths are a kind of network resources and according to requests from terminals, wavelengths are allocated or assigned to calls. In the system a wavelength used for a call is to be used for another call after the call is terminated. By supplying wavelengths to the home, a bitrate-free, protocol free or even transmission method free network can be realized. In this paper, from a viewpoint of S/N or Q factor, WAPN is evaluated with special focus on the node architecture--i. e. , from the viewpoint of node size, number of switching stages, crosstalk level,and losses, because the allowable node size is the crucial issue to decide the whole network capacity. After brief explanations of this proposed system, the model for system evaluations will be established and a node system is to be evaluated for some practical parameter values considering especially traffic characteristics of a node. As a result of this study a node system with capacity more than 100 thousands erl (about 20 Tbps throughput) can be constructed using present available technologies, which will enable us to construct large WAPN network with radius of 2,000 km and subscribers of about 50 millions.

Recent work in the area of ultrafast optical time-division multiplexed (OTDM) networking at MIT Lincoln Laboratory is presented. A scalable helical local area network or HLAN architecture, presented elsewhere as an architecture well-suited to ultrafast OTDM LANs and MANs, is considered in the context of wide area networking. Two issues arise in scaling HLAN to the wide area. The first is protocol extension, and the second is supporting the required bandwidth on the long-haul links. In this paper we discuss these challenges and describe progress made in both architecture and technologies required for scaling HLAN to the wide area.

The hybrid electrical/optical multi-chip integration technique for optical modules for optical network system has been developed. Employing the technique, a 44 broadcast-and-select type optical matrix switch module has been realized. The module consists of four sets of silica waveguide 1 : 4 splitters/4 : 1 combiners, four 4-channel arrays of polarization insensitive semiconductor optical amplifiers with spot-size converters as optical gates, printed wiring chips for electrical wiring and single mode fibers for optical signal interface on planar waveguide platform fabricated by atmospheric pressure chemical vapor deposition. All the gates and the wiring chips were mounted precisely onto the platform at once in flip-chip manner by self-align technique using AuSn solder bumps. Coupling loss between the waveguide and the SOA gate was estimated to be 4.5 dB. Averaged fiber-to-fiber signal gain, on-off ratio and polarization dependent loss for each of the signal paths was 7 dB 2 dB, more than 40 dB and 0.5 dB, respectively. High speed 10 Gb/s photonic cell switching as short as 2 nsec has been successfully achieved.

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods

Given two terms and their rewriting rules, an unreachability problem proves the non-existence of a reduction sequence from one term to another. This paper formalizes a method for solving unreachability problems by abstraction; i. e. , reducing an original concrete unreachability problem to a simpler abstract unreachability problem to prove the unreachability of the original concrete problem if the abstract unreachability is proved. The class of rewriting systems discussed in this paper is called β rewriting systems. The class of β rewriting systems includes very important systems such as semi-Thue systems and Petri Nets. Abstract rewriting systems are also a subclass of β rewriting systems. A β rewriting system is defined on axiomatically formulated base structures, called β structures, which are used to formalize the concepts of "contexts" and "replacement," which are common to many rewritten objects. Each domain underlying semi-Thue systems, Petri Nets, and other rewriting systems are formalized by a β structure. A concept of homomorphisms from a β structure (a concrete domain) to a β structure (an abstract domain) is introduced. A homomorphism theorem (Theorem1)is established for β rewriting systems, which states that concrete reachability implies abstract reachability. An unreachability theorem (Corollary1) is also proved for β rewriting systems. It is the contraposition of the homomorphism theorem, i. e. , it says that abstract unreachability implies concrete unreachability. The unreachability theorem is used to solve two unreachability problems: a coffee bean puzzle and a checker board puzzle.

Lots of self-tuning control schemes have been proposed for tuning the parameters of control systems. Among them, pole-assignment schemes have been widely used for tuning the parameters of control systems with unknown time delays. They are usually classified into two methods, the implicit and the explicit methods according to how to identify the parameters. The latter has an advantage to design a control scheme by taking account of the stability margin and control performance. However, it involves a considerably computational burden to solve a Diophantine equation. A simple scheme is proposed in this paper, which can construct a multivariable self-tuning pole-assignment control system, while taking account of the stability margin and control performance without solving a Diophantine equation.

Since the inception of optical networking, a goal has been to create an all-optical network. The rapid breakthrough for WDM in point to point links has brought this prospect considerably closer, however, at the same time, questions regarding the scalability of the all-optical network remain. In this paper, we review our recent research in this area, partly performed within the European Union project METON (METropolitan Optical Network), and discuss the all-optical approach and different optoelectronic alternatives, mainly of the 2R (reamplify and reshape) type.

Layout has strong influence on matching properties of a circuit. Current matching models, which characterize both local random non-uniformities and global systematic non-uniformities stochastically, are not adequate for the matching analysis taking the effect of layout realization into account. In order to consider topological information of layout into matching analysis, we propose a matching model which treats the random and systematic components separately. Also, we characterize the micro-loading effect, which modulates fabricated line-width according to the local density of layout patterns, into matching analysis. With these two techniques, we can perform matching analysis of CMOS circuits taking layout information into account.

Multi-input floating gate differential amplifier (FGDA) is proposed which can perform any convolution operation with differential structure and feedback loop. All operations are in the voltage mode. Only one terminal is required for the negative feedback which can suppress distortions due to mismatches of active elements. Possible applications include intelligent image sensor, where fully parallel DCT operation can be performed. A prototype chip is fabricated which is functional. A preliminary test result is reported.

Digital Signal Processors with complex arithmetic capability (DSP-C) are useful for various applications. In this paper, we propose a method for the effective implementation of specific circuits with real coefficients on DSP-C. DSP-C has special hardware such as a complex multiplier so that a complex calculation can be performed with only one instruction. First, we show that nodes with two real coefficient input branches can be implemented by complex multiplications. We apply this implementation to 2D circuits and transversal circuits with real coefficients. Next, we introduce a new computational mode (Advanced mode) and a new multiplier into PSI, a kind of DSP-C which has been proposed already, in order to process the circuits effectively. The effectiveness of the proposed method is shown by simulation in the last part.

DC offset causes performance degradation in signal processing systems especially for high-speed applications. A new offset cancellation method that relaxes the requirement for the offset of the circuit components in the differential analog data path to about 10 times larger is introduced. This method moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the final offset cancellation. It eliminates post-production adjustment such as fuse trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibration circuit is implemented in a small silicon space in a high-speed hard disk drive (HDD) channel with 0.25-µm four-layer metal CMOS process. The measured data show this method works effectively in this system.

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.