The number of DRAMs that have adopted hierarchical word-line architecture has increased as developed DRAM memory capacity has increased to more than 64 Mb. Use of the architecture enhances many kinds of DRAM performances, such as access time and fabrication process margin. However, the architecture does cause some problems. This paper describes some kinds of hierarchical word-line circuitries that have been proposed. It also describes a partial subarray activation scheme that is combined with hierarchical word-line and data-line architectures and discusses their potential and required specifications for future multi-giga bit DRAMs.

In this paper, we introduce a computational mode of a tree transducer called a bi-stage transducer and study its properties. We consider a mapping on trees realized by composition of any sequence of top-down transducers and bottom-up transducers, and call such a mapping a multi-phase tree transformation. We think a multi-phase tree transformation is sufficiently powerful. It is shown that in the case of rank-preserving transducers, a multi-phase tree transformation is realized by a bi-stage transducer.

We extend the Rabin cryptosystem to the Eisenstein and Gauss fields. Methods for constructing the complete representation class and modulo operation of the ideal are presented. Based on these, we describe the methods of encryption and decryption. This proposed cryptosystem is shown to be as intractable as factorization, and recently presented low exponent attacks do not work against it.

It is shown that two-dimensional linear phase FIR digital filters with various shapes of frequency response can be designed and realized as modular array structures free of multiplier coefficients. The design can be performed by judicious selection of two low order linear phase transfer functions to be used at each module as kernel filters. Regular interconnection of the modules in L rows and K columns conditioned with boundary coefficients 1, 0 and 1/2 results in higher order digital filters. The kernels should be chosen appropriately to, first, generate the desired shape of frequency response characteristic and, second, lend themselves to multiplierless realization. When these two requirements are satisfied, the frequency response can be refined to possess narrower transition bands by adding additional rows and columns. General properties of the frequency response of the array are investigated resulting in Theorems that serve as valuable tools towards appropriate selection of the kernels. Several design examples are given. The array structures enjoy several favorable features. Specifically, regularity and lack of multiplier coefficients makes it suitable for high-speed systolic VLSI implementation. Computational complexity of the structure is also studied.

This paper reviews analog LSI design issues for optical transmission applications; covering ultra-high-speed transmission over 10 Gb/s, multi-Gb/s systems, optical interconnection systems, and optical access. In the future system development, further advancements in not only optical device technology but also LSI technology are eagerly required. More and more sophisticated circuit design techniques are needed to lower power and operation voltage, increase integration, eliminate external elements and adjustments.

We present a general framework with which we can evaluate the flexibility and efficiency of various replay systems for parallel programs. In our approach, program monitoring is modeled by making a virtual dataflow program graph, referred to as a VDG, that includes all the instructions executed by the program. The behavior of the program replay is modeled on the parallel interpretation of a VDG based on two basic parallel execution models for dataflow program graphs: a data-driven model and a demand-driven model. Previous attempts to replay parallel programs, known as Instant Replay and P-Sequence, are also modeled as variations of the data-driven replay, i.e. the datadriven interpretation of a VDG. We show that the demand-driven replay, i.e. the demand-driven interpretation of a VDG, is more flexible in program replay than the data-driven replay since it allows better control of parallelism and a more selective replay. We also show that we can implement a demand-driven replay that requires almost the same amount of data to be saved during program monitoring as does the data-driven replay, and which eliminates any centralized bottleneck during program monitoring by optimizing the demand propagation and using an effective data structure.

In the adaptive lattice estimation process, it is well known that the convergence speed of the successive stage is affected by the estimation errors of reflection coefficients in its preceding stages. In this paper, we propose block estimation methods of two-dimensional (2-D) adaptive lattice filter. The convergence speed of the proposed algorithm is significantly enhanced by improving the adaptive performance of preceding stages. Furthermore, this process can be simply realized. The modeling of 2-D AR field and texture image are demonstrated through computer simulations.

A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75. The same margins 1.1 ns of the setup time and hold time were measured for the specifications of a setup time of 2.0 ns and a hold time of 0.5 ns.

In this paper, we present a novel way to design biorthogonal and paraunitary linear phase filter banks. The square error of the perfect reconstruction of the filter bank is expressed in quadratic form of filter coefficients and the cost function is minimized by solving linear equation iteratively without nonlinear optimization. With some modifications, this method is extended to the design of paraunitary filter banks. Furthermore, the lattice structure of odd-channel paraunitary filter banks is also derived. Design examples are given to validate the proposed method.

The application of pulse-doped GaAs MESFET's to a power amplifier module is discussed in this paper. The epitaxial layer structure was redesigned to have a dual pulse-doped structure for power applications, achieving a sufficient gate-drain brakdown voltage with excellent linearity. The measured load-pull characteristics of the redesigned device for the minimum power consumption design was presented. This device was shown to have almost twice the power-added efficiency of a conventional ion-implanted GaAs MESFET. Two kinds of power amplifiers were designed and fabricated, achieving Pout of 28.6 dBm at IM3 of -40 dBc with Pdc of 8 W and Pout of 33.0 dBm at IM3 of -40 dBc with Pdc of 32 W, respectively.

We propose low Rayleigh scattering Na2O-MgO-SiO2 (NMS) glass as a candidate material for low-loss optical fibers. This glass exhibits Rayleigh scattering which is only 0.4 times that of silica glass, and a theoretical evaluation suggests that it is dominated by density fluctuation. An investigation of the optical properties of NMS glass reveals that a minimum loss of 0.06 dB/km is expected at a wavelength of 1.6 µm and that the zero-material dispersion wavelength is found in the 1.5 µm band. To establish the waveguide structure, we evaluated the feasibility of using F-doped NMS (NMS-F) glass as a cladding layer for an NMS core and found that it is suitable because it exhibits low relative scattering (e.g. 0.7) and is versatile in terms of viscosity matching. We also describe an attempt to draw optical fibers using the double crucible technique.

Multipath interconnection networks can support higher bandwidth than those of nonblocking networks by passing multiple packets to the same output simultaneously and these packets are buffered in the output buffer. The delay-throughput performance of the output buffer in multipath networks is closely related to output traffic distribution, packet arrival process at each output link connected to a given output buffer. The output traffic distributions are different according to the various input traffic patterns. Focusing on nonuniform output traffic distributions, this paper develops a new, general analytic model of the output buffer in multipath networks, which enables us to investigate the delay-throughput performance of the output buffer under various input traffic patterns. This paper also introduces Multipath Crossbar network as a representative multipath network which is the base architecture of our analysis. It is shown that the output buffer performances such as packet loss probability and delay improve as nonuniformity of the output traffic distribution becomes larger.

This paper proposes a data-localization scheduling scheme inside a processor-cluster for multigrain parallel processing, which hierarchically exploits parallelism among coarsegrain tasks like loops, medium-grain tasks like loop iterations and near-fine-grain tasks like statements. The proposed scheme assigns near-fine-grain or medium-grain tasks inside coarse-grain tasks onto processors inside a processor-cluster so that maximum parallelism can be exploited and inter-processor data transfer can be minimum after data-localization for coarse-grain tasks across processor-clusters. Performance evaluation on a multiprocessor system OSCAR shows that multigrain parallel processing with the proposed data-localization scheduling can reduce execution time for application programs by 10% compared with multigrain parallel processing without data-localization.

A modified error correction/detection scheme based on the scheme by Yi and Lee is proposed. Algebraic decoding is used to perform error correction. Error detection is performed by an absolute value test. It is shown that the proposed scheme bridges the performance gap between Yi and Lee's scheme and Forney's optimal scheme.

We describe the implementation of an iterative method with the goal of gaining a long vector length. The strategy for vectorization by means of multipoint stencils used for discretization of the partial differential equations is discussed. Numerical experiments show that the strategy that requires certain restrictions on the number of grid points in the x and y directions improves the performance on the vector supercomputer.

A brief overview is done to the development of the fiber-optic technology. These recent topics, not the commonly established techniques, are described connecting with the developments of the basic concepts and the expected applications. Some of these newly introduced ideas will become the seeds for the future development of the fiber-optic technology. These seeds include the very deep understanding of the fiber material, new concepts for the fiber characteristics, the brandnew fiber-optic devices and the fiber-optic systems and the applications.

In this paper,we propose general fast one dimensional (1-D) and two dimensional (2-D) slant transform algorithms. By introducing simple and structural permutations, the heavily computational operations are centralized to become standardized and localized processing units. The total numbers of multiplications for the proposed fast 1-D and 2-D slant transforms are less than those of the existed methods. With advantages of convenient description in formulation and efficient computation for realization, the proposed fast slant transforms are suitable for applications in signal compression and pattern recognition.

Thermally-diffused expanded core (TEC) techniques brought the fibers with the mode fields expanded by thermal diffusion of core dopants. The techniques are effective to the reduction of splice or connection losses between the different kind of fibers, and are applied to the integrations of thin film optical devices in fiber networks, the fabrications of chirped fiber gratings, and so on. In the practical use of TEC techniques, the fibers are heated high temperature of about 1650 because of a short peried of time in processing by microburners. The mode field diameter expansion (MFDE) ratio, which is defined as the ratio of the mode field diameter in the fiber section having the core expanded and that unexpanded, is desired to be more than 2.0 from the viewpoint of loss reduction in industrial uses of the TEC techniques. When the TEC techniques are applied to polarization-maintaining optical fibers (PM fibers), such as PANDA fibers, both core dopants and stress applying part (SAP) dopants diffuse simultaneously. So the MFDE ratio is less than two without mode field deformation in conventional PANDA fibers which are practically used as PM fibers. In this paper a PANDA fiber design suitable for the TEC techniques is newly proposed. The fiber has 1.28 µm cutoff wavelength and the mode field diameter is about 11 µm before core expansion at 1.3µm wavelength.

A factorization method for a string polynomial called the constant method is proposed. This uses essentially three operations; classification of monomials, gcrd (greatest common right divisor), and lcrm (least common rigth multiple). This method can be applied to string polynomials except that their constants cannot be reduced to zeros by the linear transformation of variables. To factorize such excluded string polynomials, the naive method is also presented, which computes simply coefficients of two factors of a given polynomial, but is not efficient.

In this paper we extend the p-collection problem to a flow network with lower bounds, and call the extended problem the lower-bounded p-collection problem. First we discuss the complexity of this problem to show NP-hardness for a network with path structure. Next we present a linear time algorithm for the lower-bounded 1-collection problem in a network with tree structure, and a pseudo-polynomial time algorithm with dynamic programming type for the lower-bounded p-collection problem in a network with tree structure. Using the pseudo-polynomial time algorithm, we show an exponential algorithm, which is efficient in a connected network with few cycles, for the lower-bounded p-collection problem.