A highly reliable network which can restore itself from network failures is one important concept for the future high capacity broadband network. In such self-healing network, flooding based failure-restoration algorithm is used to locate new routes and then to reroute failure traffic to that routes automatically when network failures such as link or node failures occur. Since the speed of this algorithm is degraded by the large amount of restoration messages produced by the process, such large volume messages should be reduced. In this paper, the scheme will be proposed, which reduces the large volume messages and efficiently selects alternative routes. In this scheme, the Message Wall will be used to filter useless restoration messages at the tandem nodes and Multi-Message Selecting method will be used to rapidly select a group of link-disjointed alternative routes from the feasible ones in each Flooding Wave sequence. The simulation results show that restoration messages are dramatically reduced and adequate alternative routes can be quickly found out.

High density and small diameter optical fiber cables are required in order to construct "Fiber To The Home (FTTH)" to support multi media services economically. By reducing the cable diameter and weight, it will be possible to install longer lengths of cable and use conduits more effectively. Moreover, the development of low loss multifiber connectors and joint boxes will reduce the joining time. It is expected that the achievement of the above will lead to reductions in installation and joining costs. This paper describes the design and performance of 1000-fiber single slotted core cable. Its diameter is 30 mm compared to 40 mm for currently used multi slotted core cable, and its weight is 0.85 kg/m compared to 1.4 kg/m. The reduced cable outer diameter and weight allow us to increase both the installed length from 1 to 2 km (pre-connectorized) and the maximum fiber count from 1000 to 1600 for multiple installation in a conduit. We also describe low loss 4, and 8 mechanically transferable (MT) connectors, a pulling head and a joint box. The average connection loss of those connectors is reduced from 0.35 to 0.2 dB. The cable joining time was greatly reduced from 9 to 4.5 hours by using 5 stacks of multi fiber connectors and newly developed pulling heads and a joint boxes. Finally, we describe field test results for 1000-fiber pre-connectorized cable. In field tests, this preconnectorized cable is sufficiently stable with present installation methods. These results will lead to reductions in installation and joining costs. The 1000-fiber pre-connectorized single slotted core cable is promising with regard to upgrading the access network towards FTTH.

The application of pulse-doped GaAs MESFET's to a power amplifier module is discussed in this paper. The epitaxial layer structure was redesigned to have a dual pulse-doped structure for power applications, achieving a sufficient gate-drain brakdown voltage with excellent linearity. The measured load-pull characteristics of the redesigned device for the minimum power consumption design was presented. This device was shown to have almost twice the power-added efficiency of a conventional ion-implanted GaAs MESFET. Two kinds of power amplifiers were designed and fabricated, achieving Pout of 28.6 dBm at IM3 of -40 dBc with Pdc of 8 W and Pout of 33.0 dBm at IM3 of -40 dBc with Pdc of 32 W, respectively.

We propose low Rayleigh scattering Na2O-MgO-SiO2 (NMS) glass as a candidate material for low-loss optical fibers. This glass exhibits Rayleigh scattering which is only 0.4 times that of silica glass, and a theoretical evaluation suggests that it is dominated by density fluctuation. An investigation of the optical properties of NMS glass reveals that a minimum loss of 0.06 dB/km is expected at a wavelength of 1.6 µm and that the zero-material dispersion wavelength is found in the 1.5 µm band. To establish the waveguide structure, we evaluated the feasibility of using F-doped NMS (NMS-F) glass as a cladding layer for an NMS core and found that it is suitable because it exhibits low relative scattering (e.g. 0.7) and is versatile in terms of viscosity matching. We also describe an attempt to draw optical fibers using the double crucible technique.

In this paper,we propose general fast one dimensional (1-D) and two dimensional (2-D) slant transform algorithms. By introducing simple and structural permutations, the heavily computational operations are centralized to become standardized and localized processing units. The total numbers of multiplications for the proposed fast 1-D and 2-D slant transforms are less than those of the existed methods. With advantages of convenient description in formulation and efficient computation for realization, the proposed fast slant transforms are suitable for applications in signal compression and pattern recognition.

We describe our implementation of the Hypercube variation of the Multiple Polynomial Quadratic Sieve (HMPQS) integer factorization algorithm on a Parsytec GC computer with 128 processors. HMPQS is a variation on the Quadratic Sieve (QS) algorithm which inspects many quadratic polynomials looking for quadratic residues with small prime factors. The polynomials are organized as the nodes of an n-dimensional cube. We report on the performance of our implementations on factoring several large numbers for the Cunningham Project.

In the adaptive lattice estimation process, it is well known that the convergence speed of the successive stage is affected by the estimation errors of reflection coefficients in its preceding stages. In this paper, we propose block estimation methods of two-dimensional (2-D) adaptive lattice filter. The convergence speed of the proposed algorithm is significantly enhanced by improving the adaptive performance of preceding stages. Furthermore, this process can be simply realized. The modeling of 2-D AR field and texture image are demonstrated through computer simulations.

The quality of ELTRAN wafers has been improved by pre-injection in epitaxial growth, surface treatment just before bonding, high temperature annealing at bonding, high selective etching and hydrogen annealing. The pre-injection reduces defects. The surface treatment eliminates edge-voids. The high temperature bonding dramatically reduces voids all over the wafer. Hydrogen annealing is very effective for surface flattening and boron out-diffusion. In particular, the edge-void elimination by the surface treatment just before bonding is greatly effective for enlarging the SOI area and reduces the edge exclusion down to only two mm. The gate oxide integrity is well evaluated. This process promises high yield and through-put, because each of the steps can be independently optimized.

The applicability of a boundary matching technique is presented for reconstructing the refractive-index profile of a circularly symmetric cylinder from the measurement of the scattered wave when the cylinder is illuminated by an H-polarized plane wave. The algorithm of reconstruction is based on an iterative procedure of matching the scattered wave calculated from a certain refractive-index distribution with the measured scattered-wave. The limits of reconstruction for strongly inhomogeneous lossless and lossy cylinders are numerically shown through computer simulations under noisy environment, and are compared with those in the E-wave case.

Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was discussed in previous work [1]. RPL combines advantages of both the compact size of CPL and the full voltage-swing of DPL, and gives reasonably high performance concerning both speed and power consumption. In this paper, the application and design technique of RPL on larger logic circuits and systems are reported. Parallel adders and Booth multipliers with different sizes and structures are used as examples to evaluate the functionality of the RPL gates and full adder. In addition, there is less signal skew in RPL circuits than in conventional CPL circuits when an arrangement of single-rail to dual-rail signal conversion is performed. And, RPL is found to be useful in design of high speed and high density parallel adders and multipliers.

This paper reviews the structure and electrical properties of high-quality Internal Thermal OXidation (ITOX)-processed low-dose Separation by IMplanted OXygen (SIMOX) wafers. The ITOX SIMOX process consists of three steps: low-dose oxygen implantation, high-temperature annealing, and high-temperature oxidation. The low dose makes possible a high-throughput production of SIMOX wafers. The high-temperature annealing provides a continuous buried oxide layer and reduces the dislocation density in the top silicon layer. The subsequent high-temperature oxidation thickens the buried oxide layer without any additional oxygen implantation, thus improving its electrical properties. The ITOX mechanism is also described. It is concluded that the ITOX SIMOX wafers are very useful for fabricating ULSIs.

In a fully depleted (FD) CMOS/SIMOX device, the threshold voltage can be reduced by 0.1 V while keeping the same off current as that of bulk CMOS. This enhances gate speed at low supply voltage so that lowering supply voltage reduces both active and static power consumption without additional circuits. An LSI architecture featuring a low supply voltage for internal gates and an LVTTL interface is proposed. However, to implement the architecture with FD-CMOS/SIMOX devices, there were problems which were low drain-breakdown voltage and half electrostatic discharge (ESD) hardness compared with that of bulk CMOS devices. An LVTTL-compatible output buffer circuit is developed to overcome the low drain-breakdown voltage. Cascade circuits are applied at an output stage and a voltage converter with cross-coupled PMOS is used for reducing the applied voltage from 3.3 V to 2.2 V or less. Using this output buffer together with an LVTTL-compatible input buffer, external 3.3 V signal can be converted from/to 2.0-1.2 V signal with little static current. The cascade circuit, however, weakens the already low ESD hardness of the CMOS/SIMOX circuit. The new ESD protection circuit provides robust LVTTL compatible I/O circuits. It features lateral diodes working as drain-well-diodes in bulk CMOS and protection devices for dual power supplies. A diode/MOS merged layout pattern is used for both to dissipate heat and save area. The CMOS/SIMOX ESD protection circuit is the first one to meet the MIL standard. Using 120 kgate test LSIs made on 300 kgate array with 0.25-µm CMOS/SIMOX, 0.25-µm bulk CMOS and 0.5-µm bulk CMOS, power consumptions are compared. The 0.25-µm CMOS/SIMOX LSI can operate at an internal voltage of 1.2 V at the same frequency as the 0.5-µm LSI operating at 3.3 V. The internal supply voltage reduction scheme reduces LSI power consumption to 3% of that of 0.5-µm bulk LVTTL-LSI.

Physical models for fully depleted (FD) and non-fully depleted (NFD) SOI MOSFETs are overviewed, and recent applications of them (in SOISPICE) are described, stressing the need for good physics-based accounting for the inherently coupled bipolar and MOS device features in reliable circuit design. The applications suggest that asymmetrical double-gate FD/SOI CMOS technology can be scaled below 0.1 µm, whereas the single-gate counterpart seemingly cannot be, and that the floating-body charge dynamics and the associated transient leakage current in NFD/SOI (and FD/SOI) pass transistors in memory (DRAM and SRAM) circuits can be effectively controlled by optimal device design.

A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.

This paper describes an analytic method, experimental results and simulation results for self-heating in a SOI (Silicon On Insulator) high voltage MOS transistor. The new analytic method enabled the temperature-rise caused by self-heating to be measured precisely. The temperature-rise in an operating transistor was evaluated by measuring the change of the source current against the source current without the self-heating. In advance, the relation between the temperature-rise and the current change had been prepared by measuring the current decrease when the hot-chuck temperature had been changed in iso-thermal condition. By using this method, the dependence of the temperature-rise or the current decrease on the operating condition or the thermal resistance were clarified. Furthermore, these measurement results and the thermal resistance which is calculated by a FEM analysis enabled a fully coupled electrothermal device simulation to be analyzed more precisely. The dependence of the current decrease on the buried oxide thickness were also calculated.

This paper deals with minimization of ESOPs (exclusive-or sum-of-products) which represent symmetric functions. Se propose an efficient simplification algorithm for symmetric functions, which guarantees the minimality for some subclass of symmetric functions, and present the minimum ESOPs for all 6-variable symmetric functions.

A wireless tag system has been designed and developed for maintaining and managing outdoor communication facilities. This system employs an infrared (IR) beam and an electromagnetic wave with a radio frequency (RF), and is constructed using IR-RF tags, an IR commander, and an RF receiver. The IR command radiation with strong directivity enables a maintenance operator to recognize a target facility, and the RF response without directivity enables a management system to obtain data from within a large circular area. Solar and secondary batteries are also adopted as the power module in the tag to allow easy maintenance at long intervals. IR signal communication is possible up to a distance of 9 m, and RF signal communication is possible within a circle with a radius of 9 m.

In this paper, a novel completion prediction adder is proposed. The basic concept is to predict the completion of an adder by investigating the inputs and generate completion signal for synchronization according to the completion prediction signal. This scheme greatly enhances the performance of an adder in both aspects of delay and hardware cost. Furthermore, the relative performance enhancement compared with representative synchronous adders increases as the word length of an adder becomes longer. For example, the delay-hardware product of SCPA for a 64-bit adder is 45.1% and 42.7% of those of binary carry look-ahead adder (BCLA) and binary tree carry look-ahead adder (BTCLA), respectively.

In the proposed architecture, switching system hardware resources are allocated at the equipment level rather than at the component level of LSI chips. Equipment using these resources can thus be shared between independent systems. The efficiency of system development is improved by using structural elements called functional blocks (FBs). The hardware in each FB consists of a shared part (amicroprocessor, its peripheral circuitry, and memory) and a dedicated part that implements the specific functions of the FB. Firmware loaded into the microprocessor consists of a shared part and a dedicated part that corresponds to the hardware parts. Each FB also has its own built-in autonomous testing function to test the reliability of that FB and has its own identification function. By combining these FBs, this approach can flexibly cope with various switching system configurations for plain old telephone service (POTS), integrated services digital network (ISDN), and broad-band ISDN (B-ISDN). Tests using several types of FBs showed that the shared hardware and firmware parts of an FB can be shared between blocks. An architecture based on FBs results in a platform that can handle the hardware for various systems, making it easy to construct new switching systems.

This paper proposes a synthesis method to obtain speed-independent asynchronous circuits directly from signal transition graph (STG) specifications with single cycle signals which can be non-persistent and have free-choice operations. The resulting circuits are implemented with basic gates and asynchronous latches, and operate correctly under finite but unbounded gate delays and the zero wire delay assumptions. The proposed method introduces 5 types of lock relations to implement a non-persistent STG. A non-persistent STG can be implemented if every non-persistent signal to a signal t is super-locked with t. The resulting circuits are optimized by extracting of literals, mapping onto asymmetric C-elements, etc. Experimental results show that the proposed synthesis method outperforms the existing synthesis systems such as SYN and SIS.