A fully focused Synthetic Aperture Radar (SAR) image can be obtained only if the raw data processing procedure takes into account the space-variance of the SAR system transfer function. This paper presents a nonconventional Fast Fourier Transform (FFT) algorithm which allows an efficient compensation of the space-variant effect. It is specially designed for the SAR data of the Japanese Earth Resources Satellite (JERS-1) but can be extended to different cases.

A multi-beam airborne pulsed-Doppler radar (MBR) system is presented and its clutter rejection performance compared with conventional phased array radar (PAR)'s by PRF tuning is discussed. The pulsed-Doppler radar equations taking account of the multi-beam operation are introduced and some kinds of computer simulations for seeking the conditions to get maximum signal to clutter ratio are carried out. As a results of this, it is cleared that same order of signal to clutter ratio improvement gotten in high PRF operation by conventional PAR can be realized at lower PRF operation by MBR on clutter free area, and higher clutter rejection effect, which is proportional to beam numbers, is obtained under affection of both of mainlobe and sidelobe clutters with order of beam numbers. This also means observable numbers of range bin are increased in MBR operation.

We propose a third-order low-pass notch filter realized by a single operational amplifier and a minimum number of equal-valued capacitors. As a design example we realize a Chebyshev filter with a ripple of 0.5 dB and it is shown that the experiment result is very good.

Poled polymer films doped with novel nonlinear organic materials, α-cyano unsaturated carboxylic acid (α-CUCA) derivatives, are prepared. Linear and second-order nonlinear optical properties are investigated. It is found that as the value of hyperpolarizability of the derivatives increases, the second-order nonlinear susceptibility of the film increases. Cerenkov-type second harmonic generation (SHG) of Nd: YAG laser is realized in a poled polymer waveguide doped with the α-CUCA material with a slight absorption at doubled wavelength.

String grammars (languages) have been extensively studied from 60's. On the other hand, the transformational grammar, proposed by Chomsky, contains the transformation from the set of derivation trees of context-free language to the surface set. And the grammar regarded a tree as an input sentence to some transducer. After that from latter half of 60's, the studies of acceptor, transducer, and so on, whose input is a tree, have been done extensively. In this paper we propose, as a model, a new type of transducer which translates trees into trees and investigate its fundamental properties. The model proposed here is the pushdown tree transducer (for shortly PDTT) that is an extension of the finite state tree transducer discussed by J. W. Thacher, W. C. Rounds, J. Engelfriet, and so on. The main subjects discussed here (we consider only top-down case (t-PDTT)), are as follows: (1) final state t-PDTT translation is equivalent to empty stack t-PDTT translation and vice versa, (2) for any t-PDTT, a single state t-PDTT which is equivalent to it always exists, (3) as a standard form the symmetric stack form t-PDTT is proposed and based on this, it is shown that any single state t-PDTT can be always converted into a linear stack t-PDTT, and so on.

High performances of CMOS/SOI inverter by simulations of analytical model, reducing the poly-Si gate thickness (tm), and experiments are verified and proposed. It is shown that the tm and gate oxide thickness(tox) are correlated to gate fringing capacitance, which largely influences on the Propagation Delay Time(TPD). Contributions of gate fringing capacitance to CMOS/SIMOX inverter time delay in deep submicrometer gate devices are propounded. Measurements of the fifty-one stage ring oscillator's TPDs are completed for comparison with analytical model. Simulation results by the analytical model, including Time-Dependent Gate Capacitance (TDGC) model, agree well with the experimental results at the same conditions. Simulation results are also predicted that SOI technology is promising for speed enhancement by reducing the poly-Si gate thickness, while the tox remains constant. It is concluded that the TPDs by reducing the tm to zero are improved up to about two times faster than typically fabricated ring oscillator at 350 nm of the tm in deep-submicrometer gate CMOS/SIMOX inverters at room temperature.

An analysis of wave guidance by surface-relief grating waveguides is presented for the case of oblique propagation. This analysis is based on the first-order differential equations expressing the coupling of the space harmonics and an improved differential method is applied to solve the equations in the grating region with arbitrary profile. The propagation constants are calculated for isotropic grating waveguids with sinusoidal profile and the calculated results indicate that the accurate solutions can be obtained by increasing the number of expansion terms and the number of segments. Moreover, this method is extended to the case of the analysis of obliquely propagating waves and it is shown that peculiar leaky waves and stop bands appear owing to the coupling between TE and TM waves.

This letter presents an algorithm named SPM which generates test patterns for single stuck-at faults in synchronous sequential circuits based on a product machine traversal method. The new idea presented in this letter is partitioned image computation combined with a mixed breadth-first/depth-first search. Image computation is carried out in partitioned manner by substituting constant logical values to some input variables. This brings about significant reduction in storage requirement during image computation. A test generator based on SPM achieved 100% fault efficiency for the ISCAS'89 benchmark circuits with not more than 32 flip-flops.

This letter reports in detail on the temperature-dependent signal gain characteristics of Er3+-doped optical fiber amplifiers at signal wavelengths of 1.536µm and 1.552µm. The amplifiers were pumped at 0.825µm in a temperature range of 40 to 200. The signal gain for optimum length at both wavelengths stops increasing and begins to decrease at about 80. In the temperature region below 80, both signal gains increase with fiber temperature for fibers of optimum length or less. A temperature independent length aroud the optimum length is observed from 80 to 200 for both signal wavelengths. Theoretically, the temperature dependence of the signal gain characteristics rerults from the changes in fluorescence, absorption, GSA and ESA cross sections.

In this paper, an exact algorithm for finding minimum test set which detects all testable stuck-at faults of a given combinational circit is presented. So far several heuristic algorithms for this problem are proposed, but no efficient exact algorithms are known. To solve this exactly, minimum test set problem is formalized as a minimum set covering problem, and then implicit manipulation technique using binary decision diagrams(BDDs) is applied. The algorithm presented in the paper has two contributions. One is utilization of maximal compatible fault set, which can drastically reduce the number of candidates for minimum test set. A new BDD based algorithm for extracting all maximal compatible fault sets is shown. The other is a new implicit manipulation technique handling with huge covering matrix. Actually, the algorithm using this technique can handle minimum set covrering problem with over ten thousand columns in a few minutes. Experiments using ISCAS benchmark circuits show that the algorithm is quite efficient for small(100-300 gates) circuits. A computational complexith of minimum test set problen is much higher than that of ordinary test pattern generation problem, so that practical signifcance of this method is not high. But the algorithm is still useful for evaluation of other heuristic algorithms. furthermore, this implicit manipulation technique can also be applied to other minimumset covering problems.

A modern architect can not design high performance computer architecture without thinking all factors of performance from hardware level (logic/layout design) to system level (application programs, operating systems, and compilers). For computer architecture design, there are few practical CAD tools, which support design activities of the architect. In this paper, we propose a CAD tool, called COACH, for computer architecture design. COACH supports architecture design from hardware level to system level. To make a high-performance general purpose computer system, the architect evaluates system performance as well as hardware level performance. To evaluate hardware level performance accurately, logic/layout synthesis tools and simulator are used for evaluation. Logic/layout synthesis tools translate the architecture design into logic circuits and layout pattern and simulator is used to get accurate information on hardware level performance which consists of clock frequency, the number of transistors, power consumption, and so on. To evaluate system level performance, a compiler generator is introducd. The compiler generator generates a compiler of a programming language from the desripition of architecture design. The designed architecture is simulated in the behavior level with programs compiled by the compiler, and the architect can get information on system level performance which consists of program execution steps, etc. From both hardware level performance and system level performance, the architect can evaluate and revise his/her architecture, considering the architecture from hardware level to system level. In this paper, we propose a new design methodology which uses () logic/layout synthesis tools and simulators as tools for architecture design and () a compiler generator for system level evaluation. COACH, a CAD system based on the methodology, is discussed and a prototype of COACH is implemented. Using the design methodology, two processors are designed. The result of the designs shows that the proposed design methodology are effective in architecture design.

This paper presents a Reconfigurable Machine (RM). capable of efficiently implementing a wide range of computationlly complex algorithms. Its highly flexble architecture combining FPGA's with RAM's supports a wide range of applications. Since its "gate-level programmability" allows us to implement various kinds of parallel processing techniques, RM provides a perfomance comparable to exising "special-purpose" engines. The in-circuit reconfiguration capability of FPGA's is used to reload several kinds of configuration data during power on. Thus, RM behaves itself like a general-purpose computer applicable to various kinds of applications by loading programs. A Reconfigurable Machine-(RM-) has been built as the first prototype incorporating five FPGA's and four SRAM memory banks. RM- has been applied to a multiple-delay Logic Simulator (LSIM). Employing pipeline architecture, LSIM has achieved a perfomance of l million gate events per second at 4MHz. The concept of RM is the best solution to the trade-offs between general-purpose machines and special-purpose ones. RM will be a hardware platform accelerating a wide range of applications, also offering an interesting problem in high-level synthesis.

Field distributions and energy flows of the surface waves excited in singlelayer-overcoated gratings are evaluated in order to investigate the behavior of the resonance absorption in the grating.

In the future, it will be necessary that robot technology or environmental technology has an auditory function of recognizing sound expect for speech. In this letter, we propose a recognition system for the species of birds receiving birdcalls, based on network technology. We show the first step of a recognition system for the species of birds, as an application of a recognition system for environmental sound.

Recently, there has been a lot of research on solving combinatorial problems using Binary Decision Diagrams (BDDs), which are very efficient representations of Boolean functions. We have already developed a Boolean Expression Manipulator, which calculates and reduces Boolean expressions quickly based on BDD techniques. This greatly aids our works on developing VLSI CAD systems and solving combinatorial problems. Any combinatorial problem can be described in Boolean expressions; however, arithmetic operations, such as addition, subraction, multiplication, equality and inequality, are also used for describing many practical problems. Arithmetic operations provide simple descriptions of problems in many cases. In this paper, we present an arithmetic Boolean expression manipulator (BEM-), based on BDD techniques. BEM- calculates Boolean expressions containing arithmetic operations and then displays the results in various formats. It can solve problems represented by a set of equalities and inequalities, which are dealt with using 0-1 linear programming. We show the efficient data structure based on BDD representation, algorihms for manipulating Boolean expressions with arithmetic operations, and good formats for displaying the results. Finally we present the specification of BEM- and an example of application to the 8-Queens problem. BEM- is customizable to various applicationa. It has good computation performance in terms of the total time for programming and execution. We expect BEM- to be a helpful tool in research and development on digital systems.

Monopulse technique is widely used for tracking radars. For tracking at a low elevation angle, a narrow beam is required in the elevation plane to reduce multipath signals such as gound reflections. In this case, an elliptical aperture is desired. We have developed an antenna with a high tracking accuracy and a high aperture efficiency which is composed of a monopulse feed and an elliptical aperture. In this paper we discuss a design of the feed through lens array with an elliptical aperture and a new monopulse feed. Evaluation test results of a production model proved validity of our design and showed good performance.

Weibull-distributed clutter are reviewed. Most of the clutter received by L, S, C, X and Ku band radars obey Weibull distribution. Clutter suppression techniques for Weibull clutter are also reviewed. Especially, the generalized Weibull CFAR detector is emphasized. The approch is to estimate the shape and scale parameters of the Weibull clutter using order statistics and then use them in the detector. The generalized CFAR detector transforms the Weibull clutter distribution into a normalized exponential distribution. When a target is present, the transformation produces a large error that can be used to detect the target. Actual data taken by a Ku band radar are used to compare the proposed method with another method to estimate the Weibull parameters and with the Weibull CFAR detector. Order statistics estimation requires a small number of samples and can be used to find the local value of Weibull clutter parameters and, thus, the proposed method requires less computational time to find the Weibull parameters.

We propose a high-level synthesis method that uses data path information given by a designer. The main purpose of this method is to generate a control unit, one of the most difficult aspects of hardware design. In general, designers can specify data paths easily. Therefore, we believe that basing a method on specified data path information is the best way to synthesize hardware that more closely satisfies the designer's requirements. Moreover, a datapath-constrained scheduling algorithm can perform both "scheduling" and "resource allocation" at the same time. In particular, the resource allocation explicitly decides used paths as well as functional modules in each execution state. This cannot be done with previously reported algorithms.

Reactive systems respond to internal or external stimuli and act in an event-driven manner. It is generally difficult to specify a complex reactive systems' behavior using conventional state machine formalism. One reason is that actual reactive systems are usually formed by combining plural state-machince that behave concurretly. This paper presents the State Diagram Matrix (SDM) which is a visual and hierarchical formalism of such a reactive system's behavior. SDM has two concepts. The first is matrix plane description on which 3-dimensional state space is projected. The second is state abstraction for hierarchical state-machine definition. Understandability and reliability of control software was improved as a consequence of adopting SDM for specifying disk-subsystem control requirements. The development support functions of SDM using a workstation are also described.

This paper proposes that the statistical property of the wave form obtained by a pulse type subsurface radar follows the Weibull probability density distribution. The shape parameter of this distribution is related to the underground condition. By using the shape parameter, we calculated the statistical variance. The ratio of the variance of target area to that of non-target area in invisible medium is evaluated for the effect of the radar signal processing. Over 20dB improvement, for example, can be obtained by means of Log/CFAR processing. It made clear that the cell size of processing should be selected the length corresponding to self-correlation.