Recently, high-dose implantation and low temperature annealing have become one of the key techniques in shallow junction formation. To fabricate shallow junction in quarter-micron CMOS VLSIs, it is well known being important to evaluate the transient enhanced diffusion (TED) of implanted dopants at low temperature furnace annealing, which is caused by the damages of implantation. We have newly studied the TED phenomena by a compact empirical method. This approach has merits of simplicity and better physical intuition, because we can use only minimal parameters to describe the TED phenomena. The other purpose of this work is to evaluate two-dimensional transient enhanced diffusion focusing on phosphorus implant and furnace annealing. Firstly, we defined effective diffusivity of the TED and determined extraction procedure of the model parameters. Number of the TED model parameters is minimized to two, which describe effective enhanced diffusivity and its activation energy. The parameters have been extracted from SIMS profile data obtained from samples which range 1013-31015 cm-2 and 850-950 for phosphorus implanted dose and annealing temperature, respectively. Simulation results with the extracted transient enhanced diffusion parameters show good agreements well with the SIMS data within 2% RMS-error. Critical doses for phosphorus enhanced diffusion have been determined in 950 annealing condition. No transient enhanced diffusion is observed at 950 under the implant dose of 11013 cm-2. Also the transient enhanced diffusivity is leveled off over the dose of 11014 cm-2. It is seen that the critical dose in TED phenomena might be temperature dependent to a certain extent. We have also verified that two-dimensional effect of the TED phenomena experimentally. Two-dimensional phosphorus n- layer is chosen to verify the simulation. It was concluded that the TED has isotropic nature in phosphorus n- diffusion formation.

The exact characteristic equation for the hybrid modes in Goubau line is given. By solving the equation numerically we find the hybrid modes Lnm, defined in this paper. We also examine the propagation and attenuation constants of the hybrid modes. As a result the hybrid K12 mode has the extremely low attenuation at the specific frequency similar to the hybrid K11 mode. The electric field distributions of K11 and L11 modes are plotted.

This paper describes modeling and simulation of submicron NMOSFET current drive focusing on carrier velocity-saturation effects. A new simple analytical model is proposed which predicts a significant degradation of drain current in sub- and quarter-micron NMOSFET's. Numerical two-dimensional simulations clarify that the degradation is namely caused by high lateral electric field along the channel, which leads to deep velocity-saturation of channel electrons even at the source end. Experimental data of NMOSFET's, with gate oxide thickness (Tox) of 9-20 nm and effective channel lengths (Leff) of 0.35-3.0 µm, show good agreement with the proposed model. It is found that the maximum drain current at the supply voltage of Vdd=3.3 V is predicted to be proportional to Leff0.54 in submicron NMOSFET's, and this is verified with experiments.

The performance of a drift-diffusion device simulator using massively parallel processors is improved by modifying the preconditioner for the iterative solver and by improving the initial guess for the Newton loop. A grid-to-processor mapping scheme is presented to implement the partitioned natural ordering preconditioner on the CM-5. A new preconditioner called the block partitioned natural ordering, which may include fill-ins, improves performance in terms of CPU time and convergence behavior on the CM-5. A multigrid discretization to implement a block Newton initial guess routine is observed to decrease the CPU time by a factor of two. Extensions of the initial guess routine show further reduction in the final fine grid linear iterations.

Impact ionization () in two n+-n--n+ device structures is investigated. Data obtained from self-consistent Monte-Carlo (SCMC) simulations of the devices is used to show that the average energy () of only those high energy electrons contributing to is an appropriate variable for the modeling of . A transport model allowing one to calculate is derived from the Boltzmann transport equation (BTE) and calibrated by the SCMC simulation results. The values of and the coefficient, αii, predicted by the proposed model are in good agreement with the Monte-Carlo data.

In this paper, the formulation of unified transport model is reviewed along with its implementation in a three-dimensional device simulator. The model features an accurate description of the energy exchange among electrons, holes and lattice, and is therefore suitable for self-consistently simulating thermal effects and non-stationary phenomena, as well as their possible interactions. Despite the model complexity, it is shown that the computational effort required for its solution is reasonably close to more conventional approaches. Application examples are also given, in which both unipolar and bipolar devices are simulated, discussing the relative importance of different phenomena and highlighting the simultaneous occurrence of carrier and lattice heating.

This paper briefly reviews recent studies on free-space photonic switches, and discusses classifications, applications and technical issues to be solved. The free-space photonic switch is a switch that uses light beam interconnections based on free-space optics instead of guided-wave optics. A feature of the free-space switch is its high-density three-dimensional structure that enables compact large-scale switches to be created. In this paper, the free-space switches are classified by their various attributes such as logical network configuration, path-establishment method, number of physical stages, signal-waveform transmission form, interconnection optics and so on. The logical network configuration (topological geometry or topology) is strongly related to the advantages of the free-space switches over the guided-wave switches. The path-establishment method (path-shifting/branching-and-gating) and the number of physical stages (single-stage/multistage) are related to physical switching characteristics. Signal-waveform transmission form (analog/digital) is related to switch application. Interconnection optics (imaging system/micro-beam system) is related to the density and volume of the switching fabric. Examples of the free-space switches (single-stage, analog multistage, digital multistage and photonic ATM switches) are described. Possible applications for analog switches are subscriber-line concentrators, inter-module connectors, and switching networks for parallel or distributed computer systems. Those for digital switches include multistage space-division switches in time-division circuit-switching or packet switching systems (including asynchronous transfer mode [ATM] switching system) for both communications switching systems and parallel/distributed computer systems. Technical issues of the free-space switches (system, device, assembly technique) must be solved before creating practical systems. In particular, the assembly technique is a key issue of the free-space switches.

A software package has been developed for simulating complex silicon and heterostructure devices in 3D. Device geometries are input with a mouse-driven geometric modeler, thus simplifying the definition of complex 3D shapes. Single components of the device are assembled through boolean operations. Tetrahedra are used for grid generation, since any plane-faced geometry can be tessellated with tetrahedra, and point densities can be adapted locally. The use of a novel octree-like data structure leads to oriented grids where desirable. Bad angles that prevent the convergence of the control volume integration scheme are eliminated mostly through topological transformations, thus avoiding the insertion of many redundant grid points. The discretized drift-diffusion equations are solved with an iterative method, using either a decoupled (or Gummel) scheme, or a fully coupled Newton scheme. Alternatively, generated grids can be submitted to a Laplace solver in order to calculate wire capacitances and resistances. Several examples of results illustrate the flexibility and effectiveness of this approach.

This paper presents a new method for resolving lexical (word sense) ambiguities inherent in natural language sentences. The Sentence Analyzer (SENA) was developed to resolve such ambiguities by using constraints and example-based preferences. The ambiguities are packed into a single dependency structure, and grammatical and lexical constraints are applied to it in order to reduce the degree of ambiguity. The application of constraints is realized by a very effective constraint-satisfaction technique. Remaining ambiguities are resolved by the use of preferences calculated from an example-base, which is a set of fully parsed word-to-word dependencies acquired semi-automatically from on-line dictionaries.

This paper describes a new free-space optical switch structure based on cascaded beam shifters (each consists of a liquid-crystal polarization controller array and a birefringent plate). This structure comprises 2-input, 2-output switching elements that are locally connected by links. It is applicable to a variety of switching networks, such as a Clos network. The switching network based on this structure is an analog switch that is transparent to signal format, bit rate, and modulation type, so it can handle various types of optical signals. Theoretical feasibility studies indicate that compact large-scale switches (i.e., 100-1000 ports) with relay lens systems can be implemented using beam shifters with a 0.4-dB insertion loss and a 30-dB extinction ratio. Experimental feasibility studies indicate that a 1024-cell beam shifter module with a 0.5-dB insertion loss and a 23-dB extinction ratio is possible at present. An alignment-free assembly technique using precise alignment guides is also confirmed. An experimental 8-stage, 1024-input 256-output concentrator shows low insertion loss characteristics (6.8dB on average) owing to the low-loss beam shifters and the alignment-free assembly technique. Practical switching networks mainly require the improvement of the extinction ratio of the beam shifter module and the development of a fiber pig-tailing technique. This switch structure is applicable to transparent switching networks such as subscriber line concentrators and inter-module connectors.

The power transfer characteristics of a symmetric nonlinear directional coupler (NLDC) are analyzed rigorously using the beam propagation method based on the finite difference scheme. The NLDC consists of two linear waveguides separated by a Kerr-like nonlinear gap layer. The change of nonlinear refractive index along the coupler is precisely evaluated by making use of the second-order iteration procedure with respect to a small propagation length. For the incidence of TE0 mode of the isolated linear waveguide, the highly accurate numerical results are obtained for the behavior of power transfer, and the coupling length and critical power for optical switching. The dependencies of the coupling length and critical power on the width of the gap layer and the input power levels are discussed, compared with those predicted by the coupled-mode approximations.

Junction leakage current of trench isolation devices is strongly influenced by trench configuration. The origin of the leakage current is the mechanical stress that is generated by the differential thermal expansion between the Si substrate and the SiO2 filled isolation trench during the isolation forming process. A two-dimensional mechanical stress simulation was used to analyze trench-isolated devices. The simulated distribution and magnitude of stress were found to agree with Raman spectroscopic measurements of actual devices. The stress in the deeper regions between deep trenches is likely to increase greatly as the size of devices diminishes, so it is important to reduce this stress and thus suppress junction leakage current.

The modular and growable photonic ATM switch architecture described in this paper uses both time-division and wavelength-division multiplexing technologies, so the switch capacity can be expanded in both the time and frequency domains. It uses a new implementation of output buffering scheme that overcomes the bottleneck in receiving and storing concurrent ultra fast optical cells. The capacity in one stage of a switch with this architecture can be increased from 32 gigabits per second to several terabits per second in a modular fashion. The proposed switch structure with output channel grouping can greatly reduce the amount of hardware and still guarantee the cell sequence.

This paper presents a design of low-power CMOS OTA-C filters suitable for on-chip integration of advanced monolithic system LSIs that have analog I/O and digital signal processing capability. First, we discuss the distortion of MOS cross-coupled circuits which have a quite low distortion when the MOS FETs have the square law characteristics. Considering the nonidealities of MOS FET, however, we find that the third harmonic component of signal dominates the total harmonic distortion (THD) of the cross-coupled pair circuit. We propose a new architecture to reduce the 3rd harmonic component. Low distortion operational transconductance amplifiers (OTA) which consist of the proposed low distortion cross-coupled pair are applied to the realization of OTA-Capacitor filters. The SPICE simulation shows that the THD of the filter is 0.0047% and the power dissipation is 22.6 mW.

Material representations and algorithms are presented for simulation of nanometer lithography. Organic polymer resists are modeled as collections of overlapping spheres, with each sphere representing a polymer chain. Exposure and post-exposure bake steps are modeled at the nanometer scale for both positive and negative resists. The development algorithm is based on the Poisson removal probability for each sphere in contact with developer. The Poisson removal rate for a given sphere is derived from a mass balance relationship with a macroscopic development rate model. Simulations of electron beam lithography with (poly) methyl methacrylate and Shipley SAL-601 reveal edge roughness standard deviations from 2 to 3 nm, leading to linewidth peak-to-peak 3σ variation of 15 to 22 nm. Typical simulations require about 2 MBytes and under 5 minutes on a Sun Sparc 10/41 engineering workstation.

This paper newly estimates the yield suppression for 1.5 V-1 Gbit DRAM caused by threshold voltage variation of MOSFET due to microscopic fluctuations in dopant distributions within the channel region and points out the limitation of the conventional redundancy techniques. The yield suppression is estimated for four main circuit blocks, the memory cell transfer transistor, bit line sense amplifier S/A, I/O line differential amplifier D/A, and the peripheral circuit. It is newly found that for 1.5 V-1 Gbit DRAM due to the effect of the newly estimated threshold voltage variation of MOSFET the bit failures of memory cells become the most dominant failure mode and the failure of D/A which can be ignored for 64 Mbit DRAM level can no longer be neglected. Furthermore, the novel optimized redundancy technique for replacing these failure is described.

A simulation model for arsenic diffusion in polycrystalline silicon has been developed considering dynamic dopant clustering and polysilicon grain growth kinetics tightly coupled with dopant diffusion and segregation. It was assumed that the polysilicon layer consists of column-like grains surrounded by thin grain-boundaries, so that one dimensional description is permissible for dopant diffusion. The dynamic clustering model was introduced for describing arsenic activation in polysilicon grains, considering the solubility limit increase for arsenic in a polysilicon. For a grain-growth calculation, a previous formula was modified to include a local concentration dependence. The simulation results show that these effects are significant for a high dose implantation case.

A fully three-dimensional simulation tool for modeling the ion implantation in arbitrarily complex three-dimensional structures is described. The calculation is based on the Monte Carlo (MC) method. For MC simulations of realistic three-dimensional structures the key problem is the CPU-time consumption which is primarily caused by two facts. (1) A large number of ion trajectories (about 107) has to be simulated to get results with reasonable low statistical noise. (2) The point location problem is very complex in the three-dimensional space. Solutions for these problems are given in this paper. To reduce the CPU-time for calculating the numerous ion trajectories a superposition method is applied. For the point location (geometry checks) different possibilities are presented. Advantages and disadvantages of the conventional intersection method and a newly introduced octree method are discussed. The octree method was found to be suited best for three-dimensional simulation. Using the octree the CPU-time required for the simulation of one ion trajectory could be reduced so that it only needs approximately the same time as the intersection method in the two-dimensional case. Additionally, the data structure of the octree simplifies the coupling of this simulation tool with topography simulators based on a cellular method. Simulation results for a three-dimensional trench structure are presented.

A two-dimensional self-aligned silicide (SALICIDE) model has been developed using the general-purpose process simulator OPUS. A new two-dimensional growth model is proposed. Utilizing a newly-difined effective silicide thickness, the model accounts both silicon-diffusion and metal-diffusion limited silicide growth. Silicide lateral-growth along a sidewall spacer is successfully simulated for Si-diffusion limited silicide growth. Complete MOSFET process simulation with a SALICIDE process is demonstrated for the first time.

As a general basis for constructing a cooperative and flexible dialogue system, we are interested in modelling the inference process of an agent who participates in a dialogue. For this purpose, it is natural and powerful to model it in his general cognitive framework for problem solving. This paper presents such a framework. In this framework, we represent agent's mental states in the form called Mental World Structure, which consists of multiple mental worlds. Each mental world is a set of mental propositions and corresponds to one modal context, that is, a specific point of view. Modalities in an agent's mental states are represented by path expressions, which are first class citizens of the system and can be composed each other to make up composite modalities. With Mental World Structure, we can handle modalities more flexibly than ordinary modal logics, situation theory and other representation systems. We incorporate smoothly into the structure three basic inference procedures, that is, deduction, abduction and truth maintenance. Precise definitions of the structure and the inference procedures are given. Furthermore, we explain as examples, several cooperative dialogues in our framework.