This paper presents a generalized new approach for testing interconnects (for boundary scan architectures) as well as field programmable interconnect chips (FPICs). This approach relies on a structured walking-1 test set in the sense that a structural analysis based on the layout of the interconnect system, is carried out. The proposed structural test method differs from previous approaches as it explicitly avoids aliasing and confounding and is applicable to dense as well as sparse layouts and in the presence of faults in the programmable devices of a FPIC. The proposed method is applicable to both one-step and two-step test generation and diagnosis. Two algorithms with an execution complexity of O(n2), where n is the number of nets in the interconnect, are given. New criteria for test vector compaction are proposed; a greedy condition is exploited to compact test vectors for one-step and two-step diagnosis. For a given interconnect, the two-step diagnosis algorithm requires a number of tests as a function of the number of faults present, while the one-step algorithm requires a fixed number of tests. Simulation results for benchmark and randomly generated layouts show a substantial reduction in the number of tests using the proposed approaches compared with previous approaches. The applicability of the proposed approach to FPICs as manufactured by [1] is discussed and evaluated by simulation.

This paper presents Ternary Decision Diagrams which represent sets of products. This paper also presents manipulating methods for sum-of-products forms and ringsum-of-products forms using Ternary Decision Diagrams, and gives comparison results between Ternary Decision Diagrams and Binary Decision Diagrams.

There have been many developments on neural network research, and ability of a multi-layered network for classification of multi-spectral image data has been studied. We can classify non-Gaussian distributed data using the neural network trained by a back-propagation method (BPM) because it is independent of noise conditions. The BPM is a supervised classifier, so that we can get a high classification accuracy by using the method, so long as we can choose the good training data set. However, the multi-spectral data have many kinds of category information in a pixel because of its pixel resolution of the sensor. The data should be separated in many clusters even if they belong to a same class. Therefore, it is difficult to choose the good training data set which extract the characteristics of the class. Up to now, the researchers have chosen the training data set by random sampling from the input data. To overcome the problem, a hybrid pattern classification system using BPM and Kohonens feature mapping (KFM) has been proposed recently. The system performed choosing the training data set from the result of rough classification using KFM. However, how the remotely sensed data had been influenced by the KFM has not been demonstrated quantitatively. In this paper, we propose a new approach using the competitive weight vectors as the training data set, because we consider that a competitive unit represents a small cluster of the input patterns. The approach makes the training data set choice work easier than the usual one, because the KFM can automatically self-organize a topological relation among the target image patterns on a competitive plane. We demonstrate that the representative of the competitive units by principal component analysis (PCA). We also illustrate that the approach improves the classification accuracy by applying it on the classification of the real remotely sensed data.

This paper presents a technique for disparity selection in the context of binocular pursuit. For vergence control in binocular pursuit, it is a crucial problem to find the disparity which corresponds to the target among multiple disparities generally observed in a scene. To solve the problem of the selection, we propose an approach based on histogramming the disparities obtained in the scene. Here we use an extended phase-based disparity estimation algorithm. The idea is to slice the scene using the disparity histogram so that only the target remains. The slice is chosen around a peak in the histogram using prediction of the target disparity and target location obtained by back projection. The tracking of the peak enables robustness against other, possibly dominant, objects in the scene. The approach is investigated through experiments and shown to work appropriately.

Based on a simple model for the statistical error characteristics of range sensing, a numerical scheme called renormalization is presented for optimally fitting a planar surface to data points obtained by range sensing. The renormalization method has the advantage that not only an optimal fit is computed but also its reliability is automatically evaluated in the form of the covariance matrix. Its effectiveness is demonstrated by numerical simulation. A scheme for visualizing the reliability of computation by means of the primary deviation pair is also presented.

We propose a distributed operation system platform for optical cable networks. This distributed platform is an extension of the previously proposed platform for a flexible cable network operation. The concept of the unit platform has been proposed for the distributed operation system platform. By using this concept, we discuss the system upgrade including the connection to other operation systems. We use an object-oriented software technology for designing the distributed operation system platform. The prototype system has been constructed using C++ programing language and the evaluated results are shown.

This work deals with thermal-noise modeling for silicon vertical bipolar junction transistors (BJTs) and relevant integrated circuits (ICs) operating at low currents. The two-junction BJT compact model is consistently derived from the thermal-noise generalization of the Shockley semiconductor equations developed in work which treats thermal noise as the noise associated with carrier velocity fluctuations. This model describes BJT with the Itô non-linear stochastic-differential-equation (SDE) system and is suitable for large-signal large-fluctuation analysis. It is shown that thermal noise in silicon p-n-junction diode contributes to "microplasma" noise. The above model opens way for a consistent-modeling-based design/optimization of bipolar device noise performance with the help of theory of Itô's SDEs.

In order to ensure the reliability and safety of equipment installed in process lines, it is important that maintenance and management should make efficient use of machine diagnosis techniques. Machine diagnosis by means of acoustic signals has hitherto been beset with difficulty, but there is now a strong demand that new acoustic type diagnosis equipment (utilizing acoustic signals) be developed. In response to this demand, the authors recently conducted research on diagnosis of machine faults by means of the processing of acoustic signals. In this research they were able to develop new acoustic type machine diagnosis techniques, and, using these techniques, to develop acoustic diagnosis equipment for practical use.

Ordered binary decision diagrams (OBDDs) have been widely used in many CAD applications as efficient data structures for representing and manipulating Boolean functions. For the efficient use of the OBDD, it is essential to find a good variable order, because the size of the OBDD heavily depends on its variable order. Dynamic variable reordering is a promising solution to the variable ordering problem of the OBDD. Dynamic variable reordering with the sifting algorithm is especially effective in minimizing the size of the OBDD and reduces the need to find a good initial variable order. However, it is very time-consuming for practical use. In this paper, we propose two new implementation techniques for fast dynamic variable reordering. One of the proposed techniques reduces the number of variable swaps by using the lower bound of the OBDD size, and the other accelerates the variable swap itself by recording the node states before the swap and the pivot nodes of the swap. By using these new techniques, we have achieved the speed-up ranging from 2.5 to 9.8 for benchmark circuits. These techniques have reduced the disadvantage of dynamic variable reordering and have made it more attractive for users.

The aliasing probability was analyzed for MISRs when the error probability for each input was different. A closed form expression was derived by applying the complete weight distributions of linear codes over a Galois field and its dual codes. The aliasing probability for MISRs characterized by non-primitive polynomials was also analyzed. The inner product for binary representation of symbols was used instead of multiplication over a Galois field. The results show the perfect expression for analyzing the aliasing probability of MISRs.

A continuous-wave ultrasonic Doppler system using wide field ultrasound transducers was applied to telemeter blood velocity from the carotid artery of exercising subjects. Velocity spectrogram was obtained by Hanning windowed fast Fourier transformation of the telemetered data. Distortion caused by a high-pass filter and transducers in the telemetry system was discussed in the paper. As the maximum Reynolds number in our experiment was 1478 which is smaller than the critical level of 2000, the blood flow should be laminar. Spatial velocity profiles were then reconstructed from the velocity spectrogram. In this paper, we defined a converging index Q of the velocity spectrum to measure the bluntness of the spatial velocity distribution across the blood vessel. Greater Q, the blunter the velocity profile will be. Simulation results for spatial velocity distributions of theoretical parabolic flow and Gaussian-distribution spectra with varied Q value showed that the cut-off effect by a high-pass filter of cut-off frequency fc=200Hz in our system could be ignored when the axial velocity is larger than 0.30 m/s and Q is greater than 2.0. Our experimental results, in contrast to those obtained from phantom systems by us and by Hein and O'Brien, indicate that the distribution of blood velocity is much blunter than previously thought. The Q index exceeded 10 during systole, whereas it was 0.5 in parabolic flow. The peak of Q index lagged behind that of axial blood velocity by approximately 0.02s. The phase delay of the Q index curve might be due to the time needed for the red blood cells to form the non-homogeneous distribution.

Though tree covering is an efficient algorithm for technology mapping, phase assignments on tree boundaries are not taken into consideration. Several inverter minimization algorithms have been proposed so far, but they do phase optimization before or after technology mapping, and their cost function is not to minimize the total area but to minimize the number of inverters. This paper describes a new formulation of phase optimization problem aiming to minimize the total area during the technology mapping. Cost function representing area according to each phase assignment is introduced, and tree covering algorithm is modified to handle that cost function. Edge-Valued Binary Decision Diagram is used to represent the function implicitly. Experimental results show that proposed method reduces about 10% area on average compared with a state-of-the-art logic synthesis system sis.

This paper presents testing methods for a logic synthesis system which supports the standard HDL UDL/I, focusing on conformance test to the language specification. Conformance test, to prove that the system completely satisfies the language specification, is very important to provide a unified design environment for users of CAD tools which support the language. The basic idea of our testing methods is using a logic simulator, due to a limited schedule for the test execution. We classified the test into two: unit test and integration test. Unit test is a test of each individual functionality of the system, and integration test is a test to prove that the whole system works correctly and satisfies the language specification. And we prepared and used various kinds of test data. One of them is the UDL/I Test Suite and it was also utilized to observe progress of language coverage by the system during the test execution.

This paper presents an accurate and semi-physical MOSFET substrate current model suitable for analog circuit simulations. The proposed model is valid over a wide range of the electric field present in MOSFET devices and is continuous from cut off region to saturation region. The developed model was implemented into the circuit simulator, SPICE3. Benchmark of the developed model was achieved by making comparisons between the measured data and the simulated data for MOSFET devices, push-pull CMOS inverters, a regulated cascode CMOS operational amplifier. The experimental results showed that the developed model was more accurate and computationally efficient than the conventional models.

The family Pk of graphs with proper-path-width at most k is minor-closed. It is known that the number of minimal forbidden minors for a minor-closed family of graphs is finite, but we have few such families for which all the minimal forbidden minors are listed. Although the minimal acyclic forbidden minors are characterized for Pk, all the minimal forbidden minors are known only for P1. This paper lists 36 minimal forbidden minors for P2, and shows that there exist no other minimal forbidden minors for P2.

If a general Petri net N = (S, T, F, Mo) is transition-live under Mo, it is evident that each maximal structural deadlock SDL(D) in N as well as each minimal structural deadlock MSDL (ND) in each D is also transition-live under Mo. However, since the converse of the latter of the above is not always true, it is important to obtain the conditions for this converse to be true if we want to have a useful necessary and sufficient "initial-marking-based" or "structural" liveness condition for N. Up to now, usefull and well-known structural or initial-marking-based necessary and sufficient liveness conditions of Petri nets have only been those of an asymmetric choice (AC) net and its subclasses such as an EFC net, an FC net, an FCF net, MG, and SM. However, all the above subclasses are activated only by real or virtual deadlock-trap properties which are local liveness for each minimal deadlocks; in other words, the above topics of this paper are unconditionally satisfied in those subclasses because of their special structure of nets. In this paper, a necessary and sufficient structural liveness condition for a general Petri net N with globally structural live minimal structural deadlocks is presented as follows: The next () or () is satisfied. () N has no SDL D. () If N has at least one SDL D, () or () is satisfied under the condition that each MSDL ND in N is transition-live under Mo. () N has no singular MSDL (α) (i.e., (α-) and (α-)). () If N has at least one singular MSDL (α-)((α-), resp.), every semi-MDSL ()((), resp.) NDS = (SDS, TDS, FDS, MoDS with respect to each singular MSDL (α-)((α-), resp.), is transition-live under the MoDS under the condition of "the condition (**)", where the locally structural liveness for this NDS means (1) or (2)((3), resp.) of Lemma 4-4 and "the condition (**)" is defined in Lemma 4-7 of this paper. The relationship between the above results and the liveness problem for N is also shown.

This paper applied the polarimetric filtering principle to Synthetic Aperture Radar (SAR) image sets in three possible polarimetric radar channels and compared the resultant imagery. The polarimetric radar channels in consideration here are Co-Pol, Cross (X)-pol, and Matched (M)-pol channels. Each channel has its own polarimetric characteristics for imaging. Using the formulation of the contrast enhancement factors based on the Stokes vector formalism, polarimetric enhanced images for three channels are shown using NASA JPL DC-8 AIRSAR data sets (CC0045L, Bonanza Creek, AK/USA). It is shown that the optimally enhanced Co- and X-Pol channel images play a decisive role in imaging in a complex featured background.

SEASAT synthetic aperture radar (SAR) echoes from the sea show beautiful images of storms over the ocean. However, the mechanisms by which such storm images are created have not yet been revealed very well. The core of these images is usually an echo-free hole which is attributed to the damping of the radar-detectable short gravity waves by the intense rain in the storm core. The bright area surrounding the core is believed to be caused by strong winds diverging from the downdraft which is collocated with the intense rain. The outer boundary of the bright area has been found to be associated with the classical gust front. During the Tropical Ocean Global Atmosphere/Coupled Ocean-Atmosphere Response Experiment (TOGA/COARE), continuous observations of rain by shipborne radars were carried out. One image of JERS-1 SAR taken in this period contains storms that were within the observation area of a shipborne radar. The SAR image and the rain-radar image are compared. Even though the signal-to-noise ratio of the SAR image is very low, there is good correspondence between heavy rain areas and some of the dark areas in the SAR image. The boundary of a rain-induced dark area is found to correspond approximately to the radar reflectivity factor (Z-factor) of 35dBZ or 5.5mm/h of rain.

In this paper we describe a method for resynthesizing the controller of a design for a fixed datapath with the objective of increasing the design's throughput by minimizing its total execution time. This work has tremendous potential in two important areas: one, design reuse for retargetting datapaths to new libraries, new technologies and different bit-widths; and two, back-annotation of physical design information during High-Level Synthesis (HLS), and subsequent adjustment of the design's schedule to account for realistic physical design information with minimal changes to the datapath. We present our approach using various formulations, prove optimality of our algorithm and demonstrate the effectiveness of our technique on several HLS benchmarks. We have observed improvements of up to 34% in execution time after straightforward application of our controller resynthesis technique to the outputs of HLS.

This paper describes a 600 mV single-chip MPEG2 video decoder, implemented in a 0.5 µm triple metal CMOS technology, which operates with a 3.3-volt power supply. To achieve low power consumption, a low power dual-port RAM has been developed utilizing a selective bit line precharge scheme to reduce bit line current which is suitable for use in the bit-slice array commonly found in parametric ASIC RAM macro modules. This architecture and a non-DC current sense amp make the RAM's read power consumption one-third of that of a conventional dual-port RAM. Various techniques such as multiple-clock architecture and a system clock independent from a display clock make a system clock frequency as low as possible. The video decoder has a syntax parser, so that it can handle the higher syntactic elements of MPEG2 bit streams without any host processor and decode the Main profile at Main level of MPEG2 bit streams.