This paper proposes a new class of error locating codes which corrects random single-bit errors and indicates a location of an erroneous b-bit byte which includes e-bit errors, where 2 e b, called SECSe/bEL codes. This type of codes is very suitable for an application to memory systems constructed from byte-organized memory chips because this corrects random single-bit errors induced by soft-errors and also indicates the position of the faulty memory chips. This paper also gives a construction method of the proposed codes using tensor product of the two codes, i.e., the single b-bit byte error correcting codes and the single-bit error correcting and e-bit error detecting codes. This clarifies lower bounds and error control capabilities of the proposed codes.

This paper proposes a multiple optical wideband frequency modulation system and clarifies its phase noise insensitivity. In this system, an optical carrier is phase-modulated by a conventional FM signal to generate many sidebands in optical frequency band. The n-th order sideband component yields also FM signal with frequency deviation of n times the one of original FM signal. Therefore, by selecting the high order optical sideband, the wideband optical FM signal can be obtained. Moreover, if some sidebands are simultaneously extracted and multiplied at the receiver, a wideband FM signal with larger frequency deviation and no laser phase noise can be obtained, and FM threshold extension can be realized.

Schnorr's identification scheme is the most efficient and simplest scheme based on the discrete logarithm problem. Unfortunately, Schnorr's scheme is not provably secure, i.e., the security has not been proven to be reducible to well defined intractable problems. Two works have already succeeded to construct provably secure variants of Schnorr's scheme. They have been constructed with a common approach, i.e., by modifying the formula to compute the public key so that each public key has multiple secret keys. These multiple secret keys seem to be essential for their provable security, but also give rise to a penalty in their efficiency. In this paper, we describe a new approach to constructing a provably secure variant, where we never modify the formula, and show that with our approach, we can construct a new efficient provably secure scheme.

This paper investigates the effect of crosstalk in multichannel coherent optical ASK systems. A closed-form signal-to-noise ratio (SNR) expression as a function of number of channels, channel separation, laser phase noise, intermediate frequency (IF) filter bandwidth expansion factor (α), system bit rate (Rb=1/T), and additive shot noise is presented. When the desired channel is between two channels in the electrical domain, the minimum permissible electrical domain channel spacing for a 1dB sensitivity penalty due to crosstalk is found to be 4.85Rb when α is optimum; and 8Rb when α=5 for νT=0.30 at BER=10-9. A fairly good agreement is found between the results of this work and those of a previous study.

The use of existing metallic local line facilities is being studied for providing "video on demand (VOD)" services to residential subscribers across asymmetric digital subscriber lines (ADSL). ADSL carries a high-rate channel in the downstream direction from a central office (CO) to the subscriber, and a low-rate channel in both directions on an existing 2-wire pair. Audio and video signals are compressed by the moving picture experts group's standardized algorithms (MPEG 1 and MPEG 2), and delivered to the subscriber in the high-rate channel. Control (demand and response) signals are transceived in the low-rate channel. This paper presents the line length coverage of ADSL systems given the environment of NTT's local networks. The bit rates in the downstream and upstream directions are assumed to be 1.6-9.2Mbit/s and 24kbit/s, respectively. Two types of ADSL systems are considered: transceiving ADSL signals using the plain old telephone service (POTS) line or the basic rate access (BRA; 320 kbaud ping-pong transmission system) line on the same 2-wire pair. 16-QAM, 32-QAM and 64-QAM are compared as transmission schemes. Intra-system crosstalk interference (interference between identical transmission systems) and inter-system crosstalk interference (interference between different transmission systems) with the existing digital subscriber lines (DSL) are estimated. It is shown that the inter-system crosstalk interference with BRA is most stringent, and ADSL with 16-QAM yields the best performance in NTT's local networks. This paper concludes that realizing ADSL with 16-QAM can achieve channel capacities of up to 9.2Mbit/s for fiber-in-the-feeder (FITF) access systems, but the possibility of applying ADSL to direct access systems is remote except for a restricted short haul use. Some comparisons regarding American local networks are also described.

This paper investigates the error correcting capabilities of concatenated codes employing algebraic geometry codes as outer codes and time-varying randomly selected inner codes, used on discrete memoryless channels with maximum likelihood decoding. It is proved that Gallager's random coding error exponent can be obtained for all rates by such codes. Further, it is clarified that the error exponent arbitrarily close to Gallager's can be obtained for almost all random selections of inner codes with a properly chosen code length, provided that the length of the outer code is sufficiently large. For a class of regular channels, the result is also valid for linear concatenated codes, and Gallager's expurgated error exponent can be asymptotically obtained for all rates.

We study all-to-all broadcasting in hypercubes with randomly distributed Byzantine faults. We construct an efficient broadcasting scheme BC1-n-cube running on the n-dimensional hypercube (n-cube for short) in 2n rounds, where for communication by each node of the n-cube, only one of its links is used in each round. The scheme BC1-n-cube can tolerate (n-1)/2 Byzantine faults of nodes and/or links in the worst case. If there are exactly f Byzantine faulty nodes randomly distributed in the n-cabe, BC1-n-cube succeeds with a probability higher than 1(64nf/2n) n/2. In other words, if 1/(64nk) of all the nodes(i.e., 2n/(64nk) nodes) fail in Byzantine manner randomly in the n-cube, then the scheme succeeds with a probability higher than 1kn/2. We also consider the case where all nodes are faultless but links may fail randomly in the n-cube. Broadcasting by BC1-n-cube is successful with a probability hig her than 1kn/2 provided that not more than 1/(64(n1)k) of all the links in the n-cube fail in Byzantine manner randomly. For the case where only links may fail, we give another broadcasting scheme BC2-n-cube which runs in 2n2 rounds. Broadcasting by BC2-n-cube is successful with a high probability if the number of Byzantine faulty links randomly distributed in the n-cube is not more than a constant fraction of the total number of links. That is, it succeeds with a probability higher than 1nkn/2 if 1/(48k) of all the links in the n-cube fail randomly in Byzantine manner.

Recent high-speed bipolar technologies based on SICOS (Sidewall Base Contact Structure) transistors are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. As the characteristics of the upward operated SICOS transistors are close to those of downward transistors, they can easily be applied in memory cells which have near-perfect soft-error-immunity. Newly developed process technologies for making shallow base and emitter junctions to improve circuit performance are also reviewed. Finally, complementary bipolar technology for low-power and high-speed circuits using pnp transistors, and a quasi-drift base transistor structure suitable for below 0.1 µm emitters are discussed.

Intelligent Tutoring Systems (ITS) represents a wide class of computer based tutoring systems, designed with an extensive use of the technology of modern Artificial Intelligence. Successful applications of various expert systems and other knowledge based systems of AI gave rise to a new wave of interests to ITS. Yet, many authors conclude that practically valuable achievements of ITS are rather modest despite the relatively long history of attempts to use knowledge based systems for tutoring. It is advocated in this paper that some basic obstacles for designing really successful ITS are due to the lack of well understood and sound models of the education process. The paper proposes to overcome these problems by borrowing the required models from AI and adjacent fields. In particular, the concept of Learning Levels from AI might be very useful both for giving a valuable retrospective analysis of computer based tutoring and for suggestion of some perspective directions in the field of ITS.

The traceability of data flow diagrams against structure charts is very important for large software development. Specifying if there is a relationship between a data flow diagram and a structure chart is a time consuming task. Existing CASE tools provide a way to maintain traceability. If we can extract the input-output relationship of a system from a structure chart, the corresponding data flow diagram can be automatically generated from the relationship. For example, Benedusi et al. proposed a reverse engineering methodology to reconstruct a data flow diagram from existing code. The methodology develops a hierarchical data flow diagram from dependency relationships between the program variables. The methodology, however, transforms each module in structure charts into a process in data flow diagrams. The reconstructed diagrams may have different processes with the same name. This paper proposes a transformation algorithm that solves these problems. It analyzes the structure charts and extracts the input and ouput relationships, then determines how the set of outputs depends on the set of inputs for the data flow diagram process. After that, it produces a data flow diagram based on the include operation between the sets of output items. The major characteristics of the algorithm are that it is simple, because it only uses the basic operations of sets, it generates data flow diagrams with deterministic steps, and it can generate minimal data flow diagrams. This process will reduce the cost of traceability between data flow diagrams and structure charts.

This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.

A direct calculation method of efficiency and power of FETs from d.c. characteristics determined by knee and breakdown voltages is proposed to make clear the requirements for knee and breakdown voltages of FETs under low-voltage operation of power amplifiers. It is shown from the calculation that the breakdown voltage has a greater effect on power and efficiency than the knee voltage and has to be three or more times of the operating voltage in order not to degrade efficiency under class-AB operation. A 3.3 V UHF-band 3-stage high efficiency and high power monolithic amplifier has been developed with the use of power FETs satisfying the requirements for knee and breakdown voltages under low-voltage operation. A power-added efficiency of 57.3% and a saturated output power of 31.8 dBm have been achieved for a drain voltage of 3.3 V in UHF-band. The direct calculation method of efficiency and power from d.c. characteristics, which can provide the required knee or breakdown voltage for a given efficiency, power, or bias conditions, is considered to be useful for developing power devices with various requirements for efficiency, power, and bias conditions.

The systematic treatment of speech-spectrum transformation can be obtained in terms of algebraic topology and Morse theory. Some properties of homotopy-equivalence in the transformation of 1- and 2-dimensional speech spectrum are discussed.

This letter presents SAM, a multiplexer for ATM's circuit emulation services that can precisely control the cell clumping at the connection-level. Compared with a FIFO (First In First Out) multiplexer, it also improves the connection-level diffusion and CDV (Cell Delay Variation) performance. SAM can therefore significantly increase the number of connections accepted by CAC (Call Admission Control) procedures in the subsequent multiplexer.

Tracing solution curves of nonlinear equations is an important problem in circuit simulation. In this paper, simple techniques are proposed for improving the computational efficiency of the spherical method, which is a method for tracing solution curves. These techniques are very effective in circuit simulation where solution curves often turn very rapidly. Moreover, they can be easily performed with little computational effort.

This paper proposes novel optical path accommodation design algorithms for networks wherein the number of wavelengths multiplexed into a fiber is restricted. This algorithm optimizes both optical path route and wavelength assignment in VWP/WP networks. It minimizes optical path cross-connect (OPXC) system scale in terms of incoming/outgoing fiber port numbers. A comparison in terms of required OPXC system scale between the WP and VWP schemes is demonstrated for the first time.

Time-frequency representations (TFRs) have been developed as tools for analysis of non-stationary signals. Signal dependent TFRs are known to perform well for a much wider range of signals than any fixed (signal independent) TFR. This paper describes customised and sequential versions of the signal dependent TFR proposed in [1]. The method, which is based on the use of the Radon transform at distance zero in the ambiguity domain, is simple and effective in dealing with both simulated and real data. The use of the described method for time-scale analysis is also presented. In addition, the paper investigates a simple technique for detection of noisy chirp signals using the Radon transfrom in the ambiguity domain.

In this paper we present a system for secure communications based on chaos synchronization. Unlike the existing systems for communication via chaotic synchronization, our system extracts the information at the receiver without error. A possibility for secure communications using Lorenz system is given. A practical algorithm for secret-key cryptography is suggested and is evaluated through statistical tests that have not shown any weakness. Furthermore, the algorithm is extremely simple for implementation in a program.

A 0.5 µm CMOS embedded function type gate array family with high speed modules was developed. This family has: an effective basic cell; high speed, compiled type metallized and diffused RAMs; PLL (Phase Locked Loop); and GTL (Gunning Transceiver Logic) to realize operation of over 100 MHz at 3.3 V. This paper describes the basic cell architecture and the compiled type metallized RAM. A divided MOS transistor type basic cell is effective for metallized modules such as metallized RAM and internal logic circuits. The appropriate basic cell size (height) can be decided from the viewpoints of the relationship between the number of usable basic cells and the basic cell height, and the logic circuit speed. Propagation delay time of the 2-input NAND is 200 ps at a standard load of fan out=2 and metal length=1.4 mm. For the universal ASIC, the compiled RAM is indispensable. Single port and multi-port metallized RAMs which are structured by using the basic cells are discussed. The new single port memory cell circuit which has a differential write and single end read operating method is introduced. This memory cell circuit can be realized using one basic cell. The diffused layer region of the NMOS transfer gates for the read operation is shared between neighbor memory cells. So, the capacitance of the bit line becomes smaller, and a high speed access time can be achieved. The measured access time of 1 kbits is 4.2 ns. The new multi-port memory cell circuits which have a single end write and single end read operating method are introduced. The read operating method is the same as that of the single port memory cell circuit. The access time shows very high speed operation comparable to that of the single port memory. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment.

A 0.1-µm gate-length GaAs MESFET technology is reported. A 48.3-GHz dynamic-frequency divider, and an amplifier with 20-dB gain and 17.5-GHz bandwidth are successfully fabricated by integrating over-100-GHz-cut-off frequency MESFETs using a new lightly-doped drain structure with a buried p-layer (BP-LDD) device structure.