The problem of TM-mode scattering from the finite number of rectangular notches in a parallel plate waveguide is considered. The Fourier-transform is employed to obtain simultaneous equations and the simultaneous equations are solved to obtain an analytic solution in rapidly-convergent series. Numerical computations are performed to investigate the scattering behavior in terms of frequency and notch sizes. The presented theory is applicable to the analysis of scattering from the E-plane stubs in the rectangular waveguide.

A trained sparse conjugate codebook is proposed for improving the speech quality of CELP-based coding in a noisy environment. Although CELP coding provides high quality at a low bit rate in a silent environment (creating clean speech), it cannot provide a satisfactory quality in a noisy environment because the conventional fixed codebook is designed to be suitable for clean speech. The proposed codebook consists of two sub-codebooks; each sub-codebook consists of a random component and a trained component. Each component has excitation vectors consisting of a few pulses. In the random component, pulse position and amplitude are determined randomly. Since the radom component does not depend on the speech characteristics, it handles noise better than the trained one. The trained component maintains high quality for clean speech. Since excitation vector is the sum of the two sub-excitation vectors, this codebook handles various speech conditions by selecting a sub-vector from each component. This codebook also reduces the computational complexity of a fixed codebook search and memory requirements compared with the conventional codebook. Subjective testing (absolute category rating (ACR) and degradation category rating (DCR)) indicated that this codebook improves speech quality compared with the conventional trained codebook for noisy speech. The ACR test showed that the quality of the 8 kbit/s CELP coder with this codebook is equivalent to that of the 32 kbit/s ADPCM for clean speech.

Aczel's theory of structured objects is extended under the assumption that a structured object may belong to a sort and that these sorts are partially ordered. Based on the assumption, the forms of required objects can be specified more precisely and concisely. The resulting theory provides a general principle for the construction of order-sorted ontologies and universes of structured objects. It is applicable to systems with structured objects, such as situation theory, feature-based grammars, knowledge representation, constraint logic programming and object-oriented systems.

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 µm device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.

The message level performance of error controls in data communication on ATM network is analyzed. Three layers, "a cell"(a unit of transmission), "a block"(a unit of error controls) and "a message"(a unit of transmission of user level) are considered. The error controls treated in this paper are GBN (Go-Back-N) and FEC+GBN. The cell loss process is assumed to be the two state Markov chain considering the cell loss process in ATM networks. Numerical results show that (1) the improvement of the message forwarding delay is saturated in some environments when the interface rate becomes high, (2) FEC is efficient when the burstiness of the cell loss process is small, the message length is large and the interface rate is high.

In this study, we discuss a discrete-time cellular neural network (DTCNN) and its applications including convergence property and stability. Two theorems about the convergence condition of nonreciprocal non-uniform DTCNNs are described, which cover those of reciprocal one as a special case. Thus, it can be applied to wide classes of image processings, such as associative memories, multiple visual patterns recognition and others. Our DTCNN realized by the software simulation can largely reduce the computational time compared to the continuous-time CNN.

An 8-to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate fs and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.

In this study, multimode chaos observed from two coupled chaotic oscillators with hard nonlinearities is investigated. At first, a simple chaotic oscillator with hard nonlinearities is realized. It is confirmed that in this chaotic oscillator the origin is always asymptotically stable and that the solution, which is excited by giving relatively large initial conditions, undergoes period-doubling bifurcations and bifurcates to chaos. Next, the coexistence of four different modes of oscillations are observed from two coupled chaotic oscillators with hard nonlinearities by both of circuit experiments and computer calculations. One of the modes of oscillation is a nonresonant double-mode oscillation and this oscillation is stably generated even in the case that oscillation is chaotic. Namely, for this oscillation mode, chaotic oscillation and periodic oscillation can be simultaneously excited. This phenomenon has not been reported yet, and we name this phenomenon as double-mode chaos. Finally, the beat frequency of the double-mode chaos is confirmed to be changed by varying the value of the coupling capacitor.

In this paper, we formulate and solve a discrete-time queueing problem that has two potential applications: ATM multiplexers and DQDB networks. We first consider the modeling of an ATM multiplexer. The object of the analysis is a periodic traffic stream (CBR traffic), which is one of the inputs to the multiplexer. As in previous works of the subject, we consider a memoryless background traffic input. Here, in addition to this background traffic, we take into account the influence of a high-priority traffic, which is time-correlated and requires expedited service. We analyze the influence of these two types of traffic on the statistics of the interdeparture time (jitter process) and the delay of the periodic traffic stream. We obtain their distributions in a form of z-transforms, and from these we derive closed form expressions for the average delay and the variance of the interdeparture time. Our results show that the delay and jitter are very sensitive to the burstiness of the high priority traffic arrival process. We next apply our analytical modeling to a DQDB network when some of its stations are driven by CBR sources. We can obtain interesting results concerning the influence of the physical location of a DQDB station on the jitter.

Distributed shared memory is an attractive option for realizing functionally distributed computing in a wide area distributed environment, because of its simplicity and flexibility in software programming. However, up till now, distributed shared memory has mainly been studied in a local environment. In a widely distributed environment, latency of communication greatly affects system performance. Moreover, bandwidth of networks available in a wide area is dramatically increasing recently. DSM architecture using high performance networks must be different from the case of low speed networks being used. In this paper, distributed shared memory models in a widely distributed environment are discussed and evaluated. First, existing distributed shared memory models are examined: They are shared virtual memory and replicated shared memory. Next, an improved replicated shared memory model, which uses internal machine memory, is proposed. In this model, we assume the existence of a seamless, multi-cast wide area network infrastructure - for example, an ATM network. A prototype of this model using multi-thread programming have been implemented on multi-CPU SPARCstations and an ATM-LAN. These DSM models are compared with SCRAMNetTM, whose mechanism is based on replicated shared memory. Results from this evaluation show the superiority of the replicated shared memory compared to shared virtual memory when the length of the network is large. While replicated shared memory using external memory is influenced by the ratio of local and global accesses, replicated shared memory using internal machine memory is suitable for a wide variety of cases. The replicated shared memory model is considered to be suitable particularly for applications which impose real time operation in a widely distributed environment, since some latency hiding techniques such as context switching or data prefetching are not effective for real time demands.

Throughout the paper, the proper operating of the self-routing principle in 2-D shuffle multistage interconnection networks (MINs) is analysed. (The notation 1-D MIN and 2-D MIN is applied for a MIN which interconnects 1-D and 2-D data, respectively.) Two different methods for self-routing in 2-D shuffle MINs are presented: (1) The application of self-routing in 1-D MINs by a switch-pattern preserving transformation of 1-D shuffle stages into 2-D shuffle stages (and vice versa) and (2) the general concept of self-routing in 2-D shuffle MINs based on self-routing with regard to each coordinate which is the original contribution of the paper. Several examples are provided which make the various problems transparent.

In general, a time-limited signal such as a single sinusoidal waveform framed by a frame period T can be utilized for conveying a multi-level symbol in data transmission. If such a signal is analyzed by the conventional DFT (Discrete Fourier Transform) analysis, the infinite number of frequency components with frequency spacing fD = T1 is needed. This limits the accuracy with which the original frequency of the unframed sinusoidal waverform can be identified. It is especially difficult to identify two similar framed sinusoids whose frequency spacing is narrower than fD. An analytical principle for time-limited signals is therefore proposed by introducing the concept of an Extended Frame into DFT. Waveform analysis more accurate than DFT is achieved by taking into account multiple correlations between extended frames made of an input frame signal and the element frequency components corresponding to the length of each extended frame. In this approach, it is possible to use arbitrary element frequency spacing less than fD. It also allows an element frequency to be selected as a real number times of fD, rather than as an integer times of fD that is used for DFT. With this analyzing mechanism, it is verified that an input frame signal with only the frequency components which coincide with any of the element frequencies can be exactly analyzed. The disturbance caused by the input white noise is examined. As a result, it is found that the superior noise suppression function is achieved by this method over a conventional matched filter. In addition, the error caused by using a finite number of element frequencies and the A/D conversion accuracy required for sampling an input signal are examined, and it is shown that these factors need not impede practical implementation. For this reason, this principle is useful for multi-ary transmission systems, noise tolerant receivers, or systems requiring precise filtering of time limited waveforms.

A test structure has been developed with very low-level current measurement technique and is used to evaluate a very small change of leakage current caused by the trapping and detrapping of electrons or holes. The present technique realizes detection of very low levels of leakage current (minimum detectable current is 510-17 A), which is necessary in the course of evaluating gate oxides. This technique is very useful for the evaluation of retention characteristics and stress induced degradation of gate oxides.

A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest thresh-old voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.

ElectroStatic Discharge (ESD) testing of integrated circuits subjects circuit elements to very high currents for short periods of time. A modified Transmission Line Pulse (TLP) measurement system for characterizing transistors and other circuit elements under high currents for ESD performance prediction and understanding is presented which can both stress devices and measure leakage. For the TLP system to yield useful information test structures are needed which vary the important design parameters for the circuit elements. Guidelines for transistor test structure design for use with the system are presented and demonstrated for PMOS transistors.

Soft-error immunity of a 1-V operating CMOS memory cell is described. To evaluate the immunity precisely at the supply voltage of 1 V, a multi-threshold CMOS (MTCMOS) memory scheme, which has a peripheral circuit combining low-threshold CMOS logic gates and high-threshold MOSFETs with a virtual supply line, is adopted as a test structure. A 1-kb memory was designed and fabricated with 0.5-µm MTCMOS technology and the soft-error immunity of the memory cells was evaluated. The results of an alpha-particle exposure test and a pulse laser test show that a full-CMOS memory cell has high immunity at 1-V operations.

The quality of Si substrates affecting the oxide reliability was investigated using various kinds of test structures like flat capacitor, field edge array and gate edge array. The field edge array test structure which resembles the conditions found for real device is shown to be quite effective to determine the quality of oxides. Oxide grown on a P type epitaxial layer on P+ silicon substrate shows the highest reliability in all test structures. Gettering of heavy metals and/or crystal defects by the P+ silicon substrate is the dominant mechanism for the improvement of the oxide reliability. H2 annealed silicon shows a good reliability if monitored using the flat capacitor. However, using the field edge array test structure, which is strongly influenced by real device process, the reliability of the oxide grown on H2 annealed silicon degrades.

A learning algorithm is presented for nearest neighbor pattern classifiers for the cases where mixed supervised and unsupervised training data are given. The classification rule includes rejection of outlier patterns and fuzzy classification. This partially supervised learning problem is formulated as a multiobjective program which reduces to purely super-vised case when all training data are supervised or to the other extreme of fully unsupervised one when all data are unsupervised. The learning, i. e. the solution process of this program is performed with a gradient method for searching a saddle point of the Lagrange function of the program.

Existing edge detection methods provide unsatisfactory results when contrast changes largely within an image due to non-uniform illumination. Koch et al. developed an energy function based upon the Hopfield neural network, whose coefficients were fixed by trial and error, and remain constant for the entire image, irrespective of the differences in intensity level. This paper presents an improved edge detection method for non-uniformly illuminated images. We propose that the energy function coefficients for an image with inconsistent illumination should not remain fixed, rather should vary as a second-order function of the intensity differences between pixels, and actually use a schedule of changing coefficients. The results, compared with those of existing methods, suggest a better strategy for edge detection depending upon both the dynamic range of the original image pixel values as well as their contrast.

This work addresses the problems of bit allocation and coding gain in subband coding system with non-paraunitary filter banks. Since energy conservation does not hold in non-paraunitary filter banks, the model to be adopted for quantizers is important to evaluate the output distortion introduced by subband signal quantization. To evaluate the overall distortion we start with adopting the gain plus additive noise model for quantizers, which is more reliable than the additive noise model. With this model, the expression for overall reconstruction error variance becomes so complicated that the problem of optimum bit allocation, as required for evaluation of the coding gain, must be numerically solved. So, we propose an approximation method in which we neglect the terms due to correlation among quantization errors in calculating the bit allocation but take them into consideration in evaluating the coding gain, assuming sufficiently high bitrate coding. Application of this approximation method to the SSKF subband coding systems with AR (1) input source shows that the method is very accurate even at low bit rate coding (1 bit/sample).