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20681-20700hit(22683hit)

  • A New Dynamic Channel Allocation Algorithm Effectively Integrated with Transmitting Power Control

    Ken'ichi ISHII  Susumu YOSHIDA  Tomoki OHSAWA  

     
    PAPER-Access, Network

      Vol:
    E79-B No:3
      Page(s):
    272-278

    A new dynamic channel allocation algorithm which is integrated with transmitting power control is proposed. By introducing a new threshold, referred to as TPC threshold (Transmitting Power Control threshold), which is added some margin to the threshold of channel allocation, the subsequent transmitting power control can be performed effectively. This DCA algorithm can achieve a cellular system with both high traffic capacity and high service quality such as interference frequency performance simultaneously. The computer simulation shows that this DCA algorithm improves blocking probability performance 4 times better than that of DECT system at 14 Erlang, while keeping the same interference frequency and forced termination performances.

  • A Dynamic Channel Assignment Strategy Using Information on Speed and Moving Direction for Micro Cellular Systems

    Kazunori OKADA  Duk-kyu PARK  Shigetoshi YOSHIMOTO  

     
    PAPER-Access, Network

      Vol:
    E79-B No:3
      Page(s):
    279-288

    The dynamic channel assignment (DCA) strategy proposed here uses information on the mobile station speed and direction of motion to reduce the number of forced call terminations and channel changes in micro cellular systems. This SMD (speed and moving direction) strategy is compared with the main DCA strategies by simulating a one-dimensional service area covering a road on which there are high-speed mobile stations (HSMSs) and low-speed mobile stations (LSMSs).The simulation results show that the SMD strategy has the best performance in terms of forced call termination and channel change. The performance difference between the SMD strategy and the other DCA strategies increases as cell size decreases and as HSMS speed increases. While the SMD strategy does not yield the best total call blocking rate, its total carried load is the best when cells are small and HSMS speed is high. Also, the SMD performance improves when the HSMS offered load is small and the LSMS offered load is large. Although the SMD strategy requires information on the speed and direction of each mobile station and it increases call blockings somewhat, it reduces the number of forced call terminations and channel changes considerably, which is important in micro cellular systems.

  • Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOSSRAM

    Kenichi OHHATA  Takeshi KUSUNOKI  Hiroaki NAMBU  Kazuo KANETANI  Toru MASUDA  Masayuki OHAYASHI  Satomi HAMAMOTO  Kunihiko YAMAGUCHI  Youji IDEI  Noriyuki HOMMA  

     
    PAPER-Integrated Electronics

      Vol:
    E79-C No:3
      Page(s):
    415-423

    A novel redundancy method suitable for an ultra-high-speed SRAM with logic gates is proposed. Fuse decoders are used to reduce the number of fuses, thus suppressing the access time degradation. This makes it possible to flip chip bond an SRAM with logic gates, which has a high pin count and operates at a very high frequency. To combine the new redundancy method and an ECL decoder circuit with a BiCMOS inverter, several schemes for disabling a defective cell and enabling a spare one are discussed. A 1-Mb ECL-CMOS SRAM with 120-k logic gates was fabricated using 0.3-µm BiCMOS technology. This SRAM consists of 16 RAM macros, and the RAM macro had an access time of only 0.65 ns. The access time degradation after repair was less than 50 ps.

  • Particle Growth Caused by Film Deposition in VLSI Manufacturing Process

    Yoshimasa TAKII  Yuichi MIYOSHI  Yuichi HIROFUJI  

     
    PAPER-Particle/Defect Control and Analysis

      Vol:
    E79-C No:3
      Page(s):
    312-316

    In order to simulate the mechanism of particle growth by film deposition, imaginary-particle formation method has been newly developed. By using this formation method, the particle size, the particle height and the position of particle on a wafer could be controlled very easily. In this study, the imaginary-particles of various size larger than 0.15 micron and various height were formed on a wafer. By using these imaginary-particles, the effects of a deposition method, a film thickness, a particle size and a particle height upon the particle growth were investigated. As deposition methods, low pressure CVD method, plasma CVD method and sputtering method were compared. As a result, in all deposition method, it's clear that the particle growth doesn't depend on the initial size, and is proportional to the film thickness. Their particle growth rates are characterized by the deposition method, and their values are 1.9, 1.1 and 0.64 in low pressure CVD, plasma CVD and sputtering method, respectively. These values can be explained by the step coverage decided by the deposition method. Furthermore, the particle growth on imaginary-particle was compared with that on the real-particle. It is clear that the growth mechanism of the real-particle is closely similar to that of imaginary-particle, and the study by use of the imaginary-particle is very effective to make clear the mechanism of particle growth. Therefore, the particle size which should be controlled before deposition process is necessary to be decided by counting the particle growth shown in this paper.

  • Yield Prediction Method Considering the Effect of Particles on Sub-Micron Patterning

    Nobuyoshi HATTORI  Masahiko IKENO  Hitoshi NAGATA  

     
    PAPER-CIM/CAM

      Vol:
    E79-C No:3
      Page(s):
    277-281

    A new yield prediction model has been developed, which can successfully describe the actual chip fabrication yield. It basically consists of modeling of particles deposited on wafer surface, considering the change in their size and spatial distribution due to the subsequent processing steps and a new concept of virtual line width in pattern layouts. It is confirmed that this yield prediction model serves as an effective navigator for improvement/optimization of fabrication lines such as pointing out the process step/equipments to be modified for yield improvements.

  • Improvement of PECVD-SiNx for TFT Gate Insulator by Controlling Ion Bombardment Energy

    Yasuhiko KASAMA  Tadahiro OHMI  Koichi FUKUDA  Hirobumi FUKUI  Chisato IWASAKI  Shoichi ONO  

     
    PAPER-Device Issues

      Vol:
    E79-C No:3
      Page(s):
    398-406

    It has been revealed that ion bombardment energy and ion flux density play an essentially critical role in SiNx deposition process of PECVD in TFT-LCD production. Ion energy and ion flux density bombarding onto substrate surface are known to be extracted from waveform of RF applied to an electrode. Using this method, we investigated film quality of SiNx formed in the conventional parallel plate PECVD equipment. When N2 + H2 or N2 + Ar is employed as a carrier gas in source gas (SiH4 + NH3), we have defined normalized ion flux density as ion flux density divided by deposited SiNx molecule which must be increased to obtain high quality SiNx film while ion energy is suppressed at low level as not giving damages on the film surface. This technique has made it possible to securely form SiNx film (2500 ) featuring dielectric break-down field intensity of 8.5 MV/cm at 250 on a glass substrate with Cr gate interconnects of 1000 having vertical step struc-ture. One of the important factors to improve film quality of SiNx deposited in PECVD is to increase ion flux density while keeping ion bombardment energy low enough to protect growing surface against any damages. Using this technique inverse-staggered TFT-array featuring field effect mobility of 0.96 cm2/Vs has been demonstrated which gate insulator SiNx, non-doped a-Si: H and a-Si: H(n+) were formed continuously at the identical substrate temperature of 250.

  • Modulo 2p-1 Arithmetic Hardware Algorithm Using Signed-Digit Number Representation

    Shugang WEI  Kensuke SHIMIZU  

     
    LETTER-Computer Hardware and Design

      Vol:
    E79-D No:3
      Page(s):
    242-246

    To realize high-speed computations in a residue number system (RNS), an implementation method for residue arithmetic circuits using signed-digit (SD) number representation is proposed. Integers mp = (2p-1) known as Mersenne numbers are used as moduli, so that modulo mp addition can be performed by an end-around-carry SD adder and the addition time is independent of the word length of operands. Using a binary modulo mp SD adder tree, the modulo mp multiplication can be performed in a time proportional to log2p.

  • Object Recognition Using Model Relation Based on Fuzzy Logic

    Masanobu IKEDA  Masao IZUMI  Kunio FUKUNAGA  

     
    PAPER-Image Processing,Computer Graphics and Pattern Recognition

      Vol:
    E79-D No:3
      Page(s):
    222-229

    Understanding unknown objects in images is one of the most important fields of the computer vision. We are confronted with the problem of dealing with the ambiguity of the image information about unknown objects in the scene. The purpose of this paper is to propose a new object recognition method based on the fuzzy relation system and the fuzzy integral. In order to deal with the ambiguity of the image information, we apply the fuzzy theory to object recognition subjects. Firstly, we define the degree of similarity based on the fuzzy relation system among input images and object models. In the next, to avoid the uncertainty of relations between the input image and the 2-D aspects of models, we integrate the degree of similarity obtained from several input images by the fuzzy integral. This proposing method makes it possible to recognize the unknown objects correctly under the ambiguity of the image information. And the validity of our method is confirmed by the experiments with six kinds of chairs.

  • Performance Analysis of Voice/Data Integrated CDMA System with QoS Constraints

    Jung-Shyr WU  Jiunn-Rong LIN  

     
    PAPER-Communication Networks and Services

      Vol:
    E79-B No:3
      Page(s):
    384-391

    In this paper, we study the performance of quality-based voice/data CDMA system where new and handoff traffic are considered. A call request for handoff data queues up if the signal-to-interference ratio exceeds a predefined threshold while priority is given to handoff voice calls by reserving some channels exclusively for them. The transmission rate of data users may vary according to measured SIR value. Important performance measures of the system such as blocking probability and system capacity for voice or data calls for proposed schemes are presented and compared.

  • A Reliable Packet Transmission Method for TDMA Based Wireless Multimedia Communications

    Katsuhiko KAWAZOE  Yoshihisa SUGIMURA  Shuji KUBOTA  

     
    PAPER-Access, Network

      Vol:
    E79-B No:3
      Page(s):
    251-256

    Multiple TDMA bursts assignment between a base station and a personal terminal will be required for multimedia communications that offers high speed signal transmission such as voice and data simultaneous transmission. This paper proposes a reliable packet transmission method for TDMA based wireless multimedia communications. The proposed method employs an adaptive transmission rate control according to the packet length and a burst diversity technique is applied to improve the frame error rate of a packet. The frame error rate performance has been approximated theoretically by using fade- and infade-duration statistics of a Rayleigh fading channel and a computer simulation has been carried out for two control channels, FACCH/SACCH (Fast/Slow Associated Control CHannel) in the PHS as well as GSM. Both results indicate that the frame error rate is dramatically improved, about one order, when two bursts have different frequency and improved by about 25% when the two bursts have the same frequency.

  • Database with LSI Failure Analysis Navigator

    Takahiro ITO  Tadao TAKEDA  Shigeru NAKAJIMA  

     
    PAPER-CIM/CAM

      Vol:
    E79-C No:3
      Page(s):
    272-276

    A detabase system that provides step-by-step guidance for LSI failure analysts has been developed. This system has three main functions: database, navigator, and chip tracking. The datebase stores failure analysis information such as analysis method and failure mechanisms including image data. It also stores conditions and results of each analysis step and decisions to proceeds to the next analysis step. With 2000 failure analysis cases, data retrieval takes 6.6 seconds, a table containing 20 photos is presented in 6.5 seconds, and a different set of data can be displayed in 0.6 seconds. The navigator displays a standard analysis procedure illustrated in flow charts.The chip tracking shows where the particular chip is and what analysis it is undergoing, which is useful for the situation where many chips are simultaneously analyzed. Thus, this system has good enough functions of analysis procedure management and performance of quick data access to make failure analysis easier and more successful.

  • Cost Comparison of STM and ATM Path Networks

    Hisaya HADAMA  Tsutomu IZAKI  Ikuo TOKIZAWA  

     
    PAPER-Communication Networks and Services

      Vol:
    E79-B No:3
      Page(s):
    378-383

    In order to pave the way to B-ISDN, one of the most important issues for network providers is to identify the most efficient B-ISDN introduction strategy. This paper focuses on the costs of introducing ATM transmission systems into backbone transport networks which must provide highly reliable broad band transmission capability. In this context, the main rival to ATM is Synchronous Transfer Mode (STM); recent Synchronous Digital Hierarchy (SDH) equipment supports the establishment of advanced STM-based high speed transport networks. This paper offers a cost comparison of ATM and STM based backbone transport networks. A digital path network in STM has a hierarchical structure determined by the hierarchical multiplexing scheme employed. The minimum cost STM path network can only be determined by developing a path design method that considers all hierarchical path levels and yields the optimum balance of link cost and node cost. Virtual paths have desirable features such as non-deterministic path bandwidth and non-hierarchical and direct multiplexing capability into high speed optical transmission links. These features make it possible to implement a non-hierarchical VP network with ATM cross connect systems which can handle any bandwidth VP with a universal cell switching function. This paper shows that the non-hierarchical VP routing, which strongly minimizes link cost, can be implemented without significantly increasing node cost. Network design simulations show that the virtual path scheme, possible only in an ATM network, yields the most cost effective path network configuration.

  • Directive Antenna Diversity Reception Scheme for an Adaptive Modulation System in High Mobility Land Mobile Communications

    Takashi SUZUKI  Seiichi SAMPEI  Norihiko MORINAGA  

     
    PAPER-Modulation, Demodulation

      Vol:
    E79-B No:3
      Page(s):
    335-341

    This paper proposes a directive antenna diversity reception scheme for an adaptive modulation/time division multiple access (TDMA)/time division duplex (TDD) system to achieve high quality, high bit rate and high spectral efficient data transmission in high mobility land mobile communication environments. In mobile stations, a directive antenna is applied to equivalently reduce the observed variation speed of the fading channel. At each branch, the offset frequency (foff) and foff-canceled fading variation are estimated to improve accuracy of the propagation path characteristics estimation even in high maximum Doppler frequency (fd) environments. Computer simulation confirms that the proposed scheme can achieve successful variable rate transmission in fast fading environments.

  • Improvement of Etching Selectivity to Photoresist for Al Dry Etching by Using Ion Implantation

    Keiichi UEDA  Kiyoshi SHIBATA  Kazunobu MAMENO  

     
    LETTER-High-Performance Processing

      Vol:
    E79-C No:3
      Page(s):
    382-384

    A novel method has been developed to improve the dry etching selectivity of aluminum alloy with respect to photoresist by implanting ions into the patterned photoresist. The selectivity becomes 7.5, which is 5 times higher than that of the unimplanted case. Accordingly, this technology is very promising for fabricating multi-level interconnections in sub-half micron LSIs.

  • Sequential Dry Cleaning System for Highly-Controlled Silicon Surfaces

    Takashi ITO  

     
    PAPER-High-Performance Processing

      Vol:
    E79-C No:3
      Page(s):
    375-381

    High-performance ULSI devices require ultraclean silicon surfaces, the complete removal of native oxides, and atomic level flatness and stabilization of the cleaned surfaces against molecular contaminants. Dry cleaning techniques are an attractive alternative to conventional wet processing for future ULSI production using cluster chambers or multi-process cham-bers. Organic contaminants, including photoresist polymers, are effectively removed by photo-excited ozone cleaning. We have found photo-excited halogen radicals to be useful for removing trace metals and native oxides from silicon surfaces without damaging on silicon and silicon-dioxide surfaces. We success-fully terminated hydrogen on (100) silicon surfaces by annealing in pure hydrogen ambient. A dry cleaning system with these sequential processes will be useful in constructing fully-integrated mass-production lines of high-performance ULSI devices.

  • Efficient Characterization of Complex H-Plane Waveguide π-Junction and Cross-Junctions*

    Zhewang MA  Eikichi YAMASHITA  

     
    PAPER-Microwave and Millimeter Wave Technology

      Vol:
    E79-C No:3
      Page(s):
    444-452

    An efficient full-wave approach for the accurate characterization of a H-plane waveguide π-junction with an inductive post and a waveguide cross-junction is proposed. By employing the port reflection coefficient method (PRCM), the analysis and solution procedures of these complex waveguide junctions are greatly simplified and only the calculation of field reflections caused by the simplest waveguide step-junction discontinuities are required. The reflections are easily determined by the mode-matching technique. Scattering parameters of these junctions are provided and discussed in terms of the working frequency and the geometrical dimensions of the junctions. Calculated results are compared with those of other papers and measurements, all show good agreement.

  • Significance of Ultra Clean Technology in the Era of ULSIs

    Takahisa NITTA  

     
    INVITED PAPER

      Vol:
    E79-C No:3
      Page(s):
    256-263

    The realization of scientific manufacturing of ULSIs in the 21st century will require the development of a technical infrastructure of "Ultra Clean Technology" and the firm establishment of the three principles of high performance processes. Three principles are 1)Ultra Clean Si Wafer Surface, 2)Ultra Clean Processing Environment, and 3)Perfect Parameter controlled process. This paper describes the methods of resolving the problems inherent in Ultra Clean Technology, taking as examples issues in quarter-micron or more advanced semiconductor process and manufacturing equipment, particularly when faced with the challenges of plasma dry etching. Issues indispensable to the development of tomorrow's highly accurate and reliable plasma dry etching equipment are the development of technologies for the accurate measurement of plasma parameters, ultra clean gas delivery systems, chamber cleaning technology on an in-situ basis, and simulating the plasma chemistry.This paper also discusses the standardization of semiconductor manufacturing equipment, which is considered one of the ways to reduce the steep rise in production line construction costs. The establishment of Ultra Clean Technology also plays a vital role in this regard.

  • Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors

    Kan TAKEUCHI  Katsumi MATSUNO  Yoshinobu NAKAGOME  Masakazu AOKI  

     
    PAPER-Integrated Electronics

      Vol:
    E79-C No:2
      Page(s):
    234-242

    An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a Vcc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.

  • Design of Approximate Inverse Systems Using All-Pass Networks

    Md. Kamrul HASAN  Satoru SHIMIZU  Takashi YAHAGI  

     
    LETTER-Systems and Control

      Vol:
    E79-A No:2
      Page(s):
    248-251

    This letter presents a new design method for approximate inverse systems using all-pass networks. The efficacy of approximate inverse systems for input and parameter estimation of nonminimum phase systems is well recognized. in the previous methods, only time domain design of FIR (finite impulse response) type approximate inverse systems were considered. Here, we demonstrate that IIR (infinite impulse response) type approximate inverse systems outperform the previous methods. A nonlinear optimization technique is adopted for designing the proposed system in the frequency domain. Numerical examples are also presented to show the effectiveness of the proposed method.

  • Dyck Reductions of Minimal Linear Languages Yield the Full Class of Recursively Enumerable Languages

    Sadaki HIROSE  Satoshi OKAWA  

     
    LETTER-Automata,Languages and Theory of Computing

      Vol:
    E79-D No:2
      Page(s):
    161-164

    In this paper, we give a direct proof of the result of Latteux and Turakainen that the full class of recursively enumerable languages can be obtained from minimal linear languages (which are generated by linear context-free grammars with only one nonterminal symbol) by Dyck reductions (which reduce pairs of parentheses to the empty word).

20681-20700hit(22683hit)