The n-dimensional hypercube is a highly concurrent loosely coupled multiprocessor based on the binary n-cube topology. This paper is concerned with the following basic graph-theoretic question: given a graph G = (V, E), is it an exact n-cube? We propose an O (|E|) hypercube recognition algorithm using some new topological properties of the hypercube graph.

During the last decade the decrease in the size of computing machinery, coupled with the increase in their computing power has lend to the development of the concept of mobile computing. Effects of this new vision is currently evident in the flourishing numbers of mobile telephones and portable computing units. In this paper we briefly investigate some issues concerning the security of mobile computing systems, within the framework of the categories of mobility, disconnection, data access modes and scale of operation (Imielinski & Badrinath, 1993). In contrast to previous works which concentrate on security in wireless communications, we focus on the security of interactions which are built upon the underlying wireless communications medium. Some conclusions are presented on the future directoins for security research in mobile computing sysytems.

In estimating the performances of Distributed control Dynamic Channel Assignment (DDCA) strategies in sector cell layout systems, we find that sector cell layout systems with DDCA achieved a large system capacity. Moreover, we also indicate the problem, which is the increase of occurrences of cochannel interference, raised by using DDCA in sector cell layout systems. The new channel assignment algorithm, which is called Channel Searching on Direction of Sector (CSDS), is proposed to cope with the problem. CSDS assigns nominal channels to each sector according to their direction so that the same frequency channel tends to be used in sectors having the same direction. We show, by simulations, that CSDS is an adequate algorithm for sector cell layout systems because it significantly improves performance on co-channel interference while only slightly decreasing system capacity.

In this paper, we propose an analytic model using a semi-markov process for parallel computers which provides hardware support for a cache coherence mechanism. The model proposed here, the Semi-markov Memory and Cache coherence Interference model, can be used for the performance prediction of cache coherence based parallel computers since it can be easily applied to descriptions of the waiting states due to network contention or memory interference of both normal data accesses and cache coherence requests. Conventional analytic models using stochastic processes to describe parallel computers have the problem of numerical explosion in the number of states necessary as the system size increases even for simple parallel computers without cache coherence mechanisms. The number of states required by constructing our proposing analytic model, however, does not depend on the system size but only on the kind of cache coherence protocol. For example, the number of states for the Synapse cache coherence protocol is only 20, as is described in this paper. Using the proposed analytic model, we investigate several comparative experiments with widely known simulation results. We found that there is only a 7.08% difference between the simulation and our analytic model, while our analytic model can predict the performance of a 1,024 processor system in the order of microseconds.

We present a volume rendering algorithm which renders images at approximately two to seven times the speed of a conventional ray caster with almost no visible loss of image quality. This algorithm traverses the volume data in object order and renders the image by performing ray casting for the pixels within the footprint of the voxel (i.e., rectangular prism) being processed. The proposed algorithm supports the rendering of both single and multiple isosurfaces with arbitrary opacity values. While the projection approach to volume rendering is not new, we present an algorithm specifically designed for the perspective projection, evaluate its rendering speed for both single and multiple isosurfaces with arbitrary opacity values, and examine how efficiently it uses cache memory.

Low-power, high-speed match-detection circuits for a content addressable memory(CAM) are proposed and evaluated. The circuits consist a current supply to a match-line, a differential amplifier, and 9-MOSFET CAM cells. The implementation of these circuits made it possible to realize a 16-entry, 32-bit data-compare CAM TEG of 1.2-ns matchdetection time with 5-mW power dissipation in 10-ns cycle-time.

When a natural language specification is translated into a formal one, it is important for objects and operations appearing in the natural language specification to be appropriately classified according to the framework of data types in the formal specification. In this paper, we propose a semi-automatic method of constructing a context-free grammar (cfg) representing an assignment of data types to words in a given natural language specification. In our method, a cfg is mechanically constructed from sample sentences in a natural language specification, where the cfg represents type declarations of expressions and type hierarchy. Then, the cfg is appropriately modified by adding nonterminals/production rules that represent type inclusion relations. In this modification process, candidates for the productions to be added are presented to the user. Finally, the cfg is simplified based on structural equivalence. The result of applying this method to a part of the OSI session protocol specification (39 sentences) is also presented. There was an example in which ambiguity of anaphoric bindings was solved by type checking based on the resulting cfg.

An analysis of an imperfectly power controlled DS/CDMA slotted cellular system over the frequency selective Rician fading channel with an error correction coding is performed. The user capacity and packet throughput of reverse link are estimated to show the sensitivity to the power control error in a DS/CDMA system with Rician fading channel. The power control error are modeled with Gaussian random variables, which is a reasonable choice for its proved validity. The relative capacity decrease from the power control error in Rician channel are presented and compared with the results from flat fading channel. Performance results for the model considering multicell interference, pathloss exponent and power ratio of scattered component to direct component are presented.

This paper discusses how to derive message sequence charts (MSCs) from a set of state transition descriptions. Recently, MSC notation has received much attention in the communications software field because it graphically shows system global behavior, So MSC handling techniques are being widely studied. These studies have recommended the design a system by a set of formal MSCs in the early stages of development and then to convert them into state transition descriptions. However, it is difficult to apply those results to existing communications software products. This is because these systems are designed based on state transition descriptions and there are no formal MSCs for them. In this paper, we propose a method of deriving MSCs based on optimized reachability analysis. This method generates MCSs that avoid state explosion. A case study using Q.931 protocol shows the feasibility of this method.

Storage system in a multimedia server must satisfy two contradicting requirements: real-timeliness and large number of parallel user requests. Efficient algorithms for data placement, disk head scheduling, and request admission control schemes are needed to support the requirements. In this paper, we propose efficient schemes to maximize system resource utilization and service availability: cyclic placement scheme, subgroup retrieval scheme, and measurement-based request admission control scheme. Performance analysis through simulation revealed that the amount of system buffers required can be reduced by 70% approximately.

A 2V/120 ns flash EEPROM embedded in a microcontroller has been fabricated in 0.8 µm double-metal CMOS process technology with a simple stacked gate memory cell. To achieve low voltage and high speed operation, novel circuit technology and architecture; (a) PMOS-precharging NMOS-self-boost word line circuit with a higher voltage selector, (b) new erase algorithm for reverse operation, (c) column gate boost circuit, (d) hard-verify mode for replacing weak cells, (e) efficient redundancy of row and column lines, have been developed. A 512 kb flash EEPROM core chip incorporating these circuit techniques and architecture operate at 1.8 V and accesses data in 120 ns at 2 V and 70.

Multimedia Database Systems as the tool to extract and generate additional values from multimedia 'Contents' are discussed in this paper with putting emphasis on the mediator functions between users and contents. Firstly, we discuss about 'what to do' from the view point of four promising contents sources: 'on the network,' 'in the digital broadcasting' 'in the library' and 'in the real world.' From this view pont, four types of multimedia database systems are defined. 'What to do' for each database system is also discussed. Two concrete multimedia database systems with unique mediator functions, stream-type multimedia database platform GOLS and the intelligent access and authoring system using multiple media synchronization are proposed with experimental evaluation results and concrete multimedia database applications.

In this paper, we describe the design and implementation of a hypermedia system that has the following characteristics. First, being designed according to the Dexter hypertext reference model, it has a layered architecture and thus maintains commonality with other hypermedia systems based on the Dextermodel. Second, being designed based on the MHEG standard, it has data structures that are inherently suitable for data interchange and synchronization. Third, adopting the MIME protocol, it provides multimedia mail services. Finally, being built on top of an object-oriented DBMS, it makes it easy to represent Dexter and MHEG models and also provides efficient storage and search capabilities. The contribution of this paper is combining these characteristics to build an integrated hypermedia system reflecting reference architectures and international standard efforts.

We have fabricated a new analog memory for integrated artificial neural networks. Several attempts have been made to develop a linear characteristics of floating-gate analog memorys with feedback circuits. The learning chip has to have a large number of learning control circuit. In this paper, we propose a new analog memory SDAM with three cascaded TFTs. The new analog memory has a simple design, a small area occupancy, a fast switching speed and an accurate linearity. To improve accurate linearity, we propose a new chargetransfer process. The device has a tunnel junction (poly-Si/poly-Si oxide/poly-Si sandwich structure), a thin-film transistor, two capacitors, and a floating-gate MOSFET. The diffusion of the charges injected through the tunnel junction are controlled by a source follower operation of a thin film transistor (TFT). The proposed operation is possible that the amounts of transferred charges are constant independent of the charges in storage capacitor.

A CMOS fully balanced current-mode filter is presented. A fully balanced current-mode integrator which is the basic building block is implemented by adding a very simple common-mode-rejection mechanism to fully differential one. The fully balanced operation can eliminate even order distortion, which is one of the drawbacks in previous continuous current-mode filter. Moreover, the additional circuit can work as not only common-mode-rejection mechanism but also Q-tuning circuit which compensates lossy elements due to finite output impedance of MOS FET. A prototype fifth-order low-pass lad-der filter designed in a standard digital 0.8µm CMOS process achieved a cut-off frequency (fC) of 100MHz; fC was tunable from 75MHz to 120MHz by varying a reference bias current from 50µA to 150µA. Using a single 3V power supply with a nominal reference current of 100µA, power dissipation per one pole is 30mW. The active filter area was 0.011mm2/pole and total harmonic distortion (THD) was 0.73 [%] at 80MHz, 80µA amplitude signal. Furthermore, by adjusting two bias currents, on chip automatic both frequency and Q controls are easily implemented by typical tuning systems, for example master-slave tuning systems [1].

There have been semantics for logic programs as sets of definite clauses over sequence domains in [2],[6]. The sequence of substitutions caused by resolutions for logic programs can be captured by a fixpoint of a functional [3],[16]. In [15], a functional is regarded as a behaviour of a dataflow network, the semantics over sequence domains induces dataflow computing for logic programs. Also it may provide a transformation of logic programs to functional programs[16]. Motivated by dataflow computing constructions for logic programming, this paper deals with fixpoint semantics over sequence domains for logic programs with equations and negations. A transformation, representing deductions caused by resolutions and narrowings, is associated with a logic program with equations, modified from the operator in [18], so that it may be represented by a continuous functional over a sequence domain, and its least fixpoint is well-defined. An explicit construction of such a continuous functional of sequence variables is necessary for dataflow computing, and we should prove that the functional of sequence variables can exactly represent the transformation concerned with sets. For a general logic program, a functional is constructed over a sequence domain so that it may reflect a consistency-preserving renewal function for the pair of atom sets on the basis of the 3-valued logic approach as in [7], and [11]. It is a problem to construct the domain for the functional representing a generation of atom sets interpreted as true and negation as failure in the generation, for general logic programs. The functional is monotonic over a complete partial order and its least fixpoint is well-defined, although the least fixpoint is not always obtained by the limit of finite computing, because of the functional being not necessarily continuous.

A cavity model well suited for computed-aided design is developed to synthesize the dimensions of patches for a given resonant frequency, an input resistance and a substrate. The antennas which have been investigated are rectangular patches fed with either a microstripline or a coaxial probe.

Signal Transition Graphs (STG'S) [1] are Petrinets [2], which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets (OCN) and its prefix, called unfollding, has been proposed [3], [4]. OCN's can represent both causality and concurrency between two nodes by net stryctyre. In this paper, we propose an efficient algorithm to derive a logic function by generating sub-state space of a given STG using the structural properties of OCN. The proposed algorithm can be seem as a parallel algorithm for deriving a logic function.

When people watch such motion pictures as documentaries or educational-type films, it is very natural for them to be interested in moving objects in the movies and be eager to know the detailed information related to these object. Therefore, a mechanism that enables users to directly pick up object information from motion pictures is necessary to make a movie system feasible. For this reason, we are researching techniques on using objects in motion pictures as hypermedia anchors. We call a movie system that provides the above mechanism a video hypermedia system. An object in a motion picture can generally be considered as a complex object which includes many parts. To allow users to obtain information related to each part, a system must be able to provide anchors corresponding to each part in each complex object. For this, authors cannot help defining all anchors in all frames, since the visual status of each part varies from moment to moment. This paper presents our approach for managing objects in motion pictures for video hypermedia systems. The main feature of the proposed method is to apply computer graphic techniques to the defining of anchors for a complex object.

This paper describes methods in which natural language is used to describe video contents, knowledge of which is needed for intelligent video manipulation. The content encoded by natural language is extracted by a language analyzer in the form of subject-centered dependency structures which is a language-oriented structure, and is combined in an incremental way into a single structure called a multi-path index tree. Content descriptors and their inter-relations are extracted from the index tree in order to provide a high speed retrieval and flexibility. The content-based video index is represented in a two-dimensional structure where in the descriptors are mapped onto a component axis and temporal references (i.e., video segments aligned to the descriptors) are mapped onto a time axis. We implemented an experimental image retrieval systems to illustrate the proposed index structure 1) has superior retrieval capabilities compare to those used in conventional methods, 2) can be generated by an automated procedure, and 3) has a compact and flexible structure that is easily expandable, making an integration with vision processing possible.