In this paper, a simple method to investigate the dynamics of continuous-time neural networks based on the force (kinetic vector) derived from the equation of motion for neural networks instead of the energy function of the system has been described. The number of equilibrium points and limit cycles of one-dimensional neural networks with the asymmetric cyclic connection matrix has been investigated experimently by this method. Some types of equilibrium points and limit cycles have been theoretically analyzed. The relations between the properties of limit cycles and the number of connections also have been discussed.

In this paper, a post-layout optimization technique for power dissipation and timing of cell-based Bipolar ECL LSIs is proposed. An ECL LSI can operate at a frequency of a few GHz but the power dissipation is very high compared to CMOS LSIs, which makes the systems using ECL quite expensive. Therefore it is crucial to develop of CAD techniques that minimize the power dissipation of an ECL LSI without decreasing its performance. To begin with, power and delay models of an ECL gate are presented as functions of its switching current. The power dissipation is a linear function of the switching current and the delay time is its hyperbolic function. These functions are obtained considering the post-layout interconnect capacitance and resistance to make the optimization results accurate enough. Using the delay model, a set of timing constraints specifying the max/min cell delay and the clock skew are extracted. This set of constraints in then given to a nonlinear programming package. The objective functions are clock skew time, the clock cycle time and the power dissipation, which are optimized in this order. With the minimum delay and hold constraints, the problem is not convex so that conventional convex programming approach cannot be used. As a result of the optimization, the switching currents for cells are obtained. These are realized within cells by regulating programmable resistors", which is a special feature of our ECL cell library. Since the above optimization is carried out after the placement and routing of the circuit, it can take accurate delay and power estimation into consideration. Experimental results show more than 40% power reductions for circuits including a real communication system chip, compared to the max power versions. The clock cycle time was maintained or even made faster due to the efficient clock skew optimization.

We propose a speech recognition method using fusion of auditory and visual information for accurate speech recognition. Since we use both auditory information and visual information, we can perform speech recognition more accurately in comparison with the case of either auditory information or visual information. After processing each information by HMM, they are fused by linear combination with weight coefficient. We performed experiments and confirmed the validity of the proposed method.

A algorithm for designing a pattern classifier, which uses MDL criterion and a binary data structure, is proposed. The algorithm gives a partitioning of the range of the multi-dimensional attribute and gives an estimated probability model for this partitioning. The volume of bins in this partitioning is upper bounded by ο((log N/N)K/(K+2)) almost surely, where N is the length of training sequence and K is the dimension of the attribute. The convergence rates of the code length and the divergence of the estimated model are asymptotically upper bounded by ο((log N/N)2/(K+2)). The classification error is asymptotically upper bounded by ο((log N/N)1/(K+2)). Simulation results for 1-dimensional and 2-dimensional attribute cases show that the algorithm is practically efficient.

In general, a learning machine will behave better as the number of training examples increases. It is important to know how fast and how well the behavior is improved. The average prediction error, the average of the probability that the trained machine mispredicts the output signal, is one of the most popular criteria to see the behavior. However, it is not easy to evaluate the average prediction error even in the simplest case, that is, the linear dichotomy (perceptron) case. When a continuous deterministic dichotomy machine is trained by t examples of input-output pairs produced from a realizable teacher, these examples limits the region of the parameter space which includes the true parameter. Any parameter in the region can explain the input-output behaviors of the examples. Such a region, celled the admissible region, forms in general a (curved) polyhedron in the parameter space, and it becomes smaller and smaller as the number of examples increases. The present paper studies the shape and volume of the admissible region. We use the stochastic geometrical approach to this problem. We have studied the stochastic geometrical features of the admissible region using the fact that it is dual to the convex hull the examples make in the example space. Since the admissible region is related to the average prediction error of the linear dichotomy, we derived the new upper and lower bounds of the average prediction error.

Leaky Bucket based traffic parameters are widely used for traffic declaration and enforcing in an ATM network. In this paper, we investigate the characteristics of the system that every traffic source is policed by a dual leaky bucket before entering the network. In addition to mean cell rate, peak cell rate of traffic is also taken into consideration. We find the worst output pattern from the dual leaky bucket and derive the performance bound of maximum cell loss ratio encountered in the multiplexer. It is obtained as every source transmits cells according to the criteria for extreme synchronous transmission in a coincident token-generating condition.

This paper is concerned with bandwidth reservation for circuit groups which handle calls requesting asymmetric forward and backward multi-connections. A model of circuit group with sub-group configuration is treated, and two types of the bandwidth reservation schemes for the model are studied in this paper. One is a global scheme with monitoring the whole circuit group, and the other is a local scheme with monitoring each sub-group independently. The problems of optimizing the reservation parameters are formulated, and optimization methods for the problems are proposed. Numerical example are presented, and effectiveness of the reservation schemes with using the optimized parameters is numerically examined.

One of the important properties of multihop network is the mean internodal distance to evaluate the transmission delay, and the connective semi-random network achieves smaller mean internodal distance than other networks. However, the results are shown only by computer simulation and no theoretical analysis is investigated. Moreover, the network connective probability of the connective semi-random network is relatively small. In this paper, we propose the restricted connective semi-random network whose network connective probability is larger than that of the conventional connective semi-random network. And we theoretically analyze the mean internodal distance and the network connective probability of these two networks. It is shown that if the restriction is loose, the mean internodal distance of our model is almost the same as that of the conventional model, whereas the network connective probability of our model is larger than that of the conventional model. Moreover, the theoretical analyzed results of the mean internodal distance agree well with the simulated results in the conventional model and our model with small restriction.

A tunnel film(9 nm thick) formed by a rapid thermal oxidation in dry oxygen-rapid thermal nitridation in NH3-rapid thermal oxynitridation in N2O (ONN) sequence is applied to a stacked-gate flash memory cell, in which writing and erasing are carried out by Fowler-Nordheim tunneling at a drain and at a channel, respectively. The writing, erasing, endurance, disturbance and retention characteristics of the memory cells with ONN tunnel films are, for the first time, compared to those of the memory cells with conventional tunnel films such as dry oxide, N2O-oxynitride and reoxidized nitrided oxide tunnel films. No significant difference of the writing and erasing characteristics was observed among the memory cells with the various tunnel films. However, the amount of Vth window narrowing in the endurance characteristics of the memory cells with ONN (-12.9%) and reoxidized nitrided oxide(-11.4%) tunnel films were much smaller than those of the memory cells with RTO(-34.0%) and NO (-38.2%) after 106 write/erase cycles. Furthermore, the decrease in Vth in the drain disturbance characteristics of the memory cells with ONN tunnel films (21.2%) after weak electron-ejecting stress of 105 cycles was smaller than those of the memory cells with the other films(51.4-64.4%). The retention characteristics of the memory cells with ONN tunnel films under the thermal stress of 200, 5.9105 sec were superior(ΔVth=-2.1%) to those of the memory cells with the other films(ΔVth=-5.4 - -8.2%). The reasons of these findings are because ONN films exhibit smaller number of charge traps and interface states induced by write/erase cycle stress, and suppress leakage curent stimulated by the weak electron-ejecting bias and the thermal stress, compared to the dry oxide, the N2O-oxynitride and the reoxidized nitrided oxide. ONN films are found to be suitable for use as tunnel films of fiash memory cells.

We have investigated the gain and noise figure characteristics of a Nd-doped silica single-mode fiber amplifier (NDFA) at 1.06 µm which is applicable to various systems using a Nd: YAG laser light source at 1.06 µm, such as free-space laser communications, a fiber sensing system, and a lidar system. A fluorescence spectrum observation of the Nd-doped fibers with various co-dopants shows that the Nd-A1 co-doped fiber is suitable for realizing a high-gain amplifier for the 1.06-µm wavelength region. The pump wavelength tolerance at around 0.81 µm , the gain bandwidth and the sufficient value of the Nd concentration and length product for achieving maximum small signal gain are clarified. A noise figure of almost 3 dB and small signal gain of more than 30 dB are attained by 50-mW pump power. The unique four-level system characteristics, even in low pumppower conditions, provide low noise amplification in the NDFA. These gain and noise characteristics are well described by a simple theoretical model. We also demonstrated high-power operation of the NDFA with four pump LD modules adoptinga polarization-multiplexing technique. More than 100-mW signal output power is available for 1-mW signal input power at 200mW launched pump power. These features of the NDFA as a compact, polarization-independent, spatial-beam -distortion-free amplifier, will allow it to replace the solid sate laser in various applications using a Nd: YAG laser light source at 1.06µm.

This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.

Special memory and embedded memories used in a newly designed MPEG2 decorder LSI are described. Orthogonal memory, which has a functionality of parallel-to-serial transposition, is employed in a IDCT(Inverse Discrete Cosine Transform) block for small area and low-power. The orthogonal memory realizes the special pupose with 50% of the area and the power compared with using flip-flop array. FIFO's and other dual-port memories are designed by using a single-port RAM operated twice in one clock cycle to reduce cost. Flip-Flop cell is one of the important memory elements in the MPEG environment, and is also improved for the low-cost optimizing functionality for video processing. The area and power of the fabricated MPEG2 decoder chip are reduced by 20% using these techniques. As for testability, direct test mode is implemented for small area. An instruction RAM is placed outside the pad area in parallel to a normal instruction ROM and activated by Al-masterslice for extensive debugging and an early sampling. Other memory related techniques and the key features of the decoder LSI are also described.

A crossing charge recycle refresh(CCRR) scheme and a serial charge recycle refresh(SCRR) scheme are proposed for the large capacity DRAMs with hierarchical bit-line architecture to reduce main bit-line charging current. A separated driver sense-amplifier(SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense-amplifiers. These circuits are applied to an experimental 1-Gb DRAM, which achieves reduction of main bit-line charging current to 37.5%.

A 0.96µm2 NAND-structured stacked capacitor cell has been achieved using conventional i-line photolithography and a 0.4µm design rule. Memory cell patterns for critical levels have been designed with a simple lineand-space configuration and a completely repeated hole arrangement for large lithography process margin. The word-line pitch and bit-line pitch are 0.9µm and0.95µm, respectively. In order to obtain sufficient storage capacitance and large alignment margin, a self-aligned cylindrical stacked capacitor and bit line plug fabrication process has been developed. These new technologies have enabled storage capacitance of 15 fF/cell with a 0.5µm capacitor height and a 5 nm equivalent SiO2 film thickness for nitride-top oxide(NO) film in the bit-line over capacitor(BOC) structure. Due to its lithography-oriented cell design and self-aligned process procedure, the present cell is a promising candidate for 256 Mb DRAM and beyond.

We report two new timing control methods for high-speed synchronous interfaces in view of their application to high-speed synchronous DRAMs. These two new circuits are the measure-controlled DLL and the register-controlled DLL.We quantitatively analyzed the minimum operational cycle time for a synchronous interface, and related the minimum bus cycle time to two factors; the bus-to-clock timing skew, and the unit delay time of the DLL. Based on this analysis, we concluded that the I/O performance can be beyond 400 MHz by suppressing both factors to less than 200 ps.

A new source line routing architecture features a blanket-like source line made of double aluminum layers by utilizing a pure tungsten metal layer as the local interconnection layer in the peripheral region. The relaxed pitch of the signal lines improves the RC time delay constant of the signal lines and gives stable Vcc and Vss levels throughout the chip. Furthermore, this architecture brings about an 8% area reduction of the peripheral region in 256 Mb DRAMs with high performance,when used in collaboration with hierarchical bit-line architecture.

Ferroelectic nonvolatile technology comprises the ferroelectric material technology, the process technology and the circuit technology. Bi based layered Perovskyte ferroelectric material, SrBi2Ta2O9, so called "Y 1," has superior characteristics in terms of endurance and nonvolatile properties, which is confirmed by a 256kbit ferroelectric nonvolatile memory. Critical issues regarding the ferroelectric process are reviewed. The lT/lC cell configuration which is essential for a high density memory and the reference voltage generator employed in the 256 k memory are described as is the architecture to reduce the power consumption of the memory.

The Michelson-interferometer (MI) optical resonator has been applied, together with physical interests, to a low pressure and slow-flow type CO2 laser for specifying the system to a probe laser source. The fundamental characteristics online-selection, oscillation power and transverse mode are also investigated in comparison to the CO2 laser obtained for various resonators such as an open-ended reflective-multiple interferometer (RMI), an open-sided MI, a Fox-Smith interferometer and soon. Consequently, it is confirmedthat the MI type laser proposed can be one of the promising scheme, without losing oscillation power much and transverse mode quality as a probe laser towards lineshape (or laser) parameter analysis. Translating one of the MI mirror by a slight distance on the order of a micron meter along the gain axis, we can not only switch either a single rotational-vibrational line or combination of multiple lines, but also obtain different combination of lines by translating a large amount of the translation distance of the order of 100 µm. Moreover, elimination of one of the side-mirrors in the MI resonator enables us to switch the oscillation lines at the expense of some output power.

The data retention characteristics for Flash EEPROM degrade after a large number of write and erase cycles due to the increase of the tunnel oxide leakage current. This paper proposes a new write/erase method which uses a reverse polarity pulse after each erase pulse. By using this method, the leakage current can be suppressed. As a result, the read disturb time after 105cycles write/erase operation is more than 10 times longer in comparison with that of the conventional method. Moreover, using this method, the endurance cycle dependence of the threshold voltage after write and erase operation is also drastically improved.

This paper describes a newly developed sensing scheme with a bit-by-bit program verify technique for NAND flash disk systems. This sensing scheme achieves good noise immunity for large capacitive coupling between bitlines, and makes NAND flash memories operable for flexible power supply voltages including both 3.3V and 5V. A highly reliable read operation is performed for power supply voltages above 3V and a bitline-bitline coupling ratio below 50%. The sensing scheme also achieves an intelligent page copy function with 20% reduction in time and without external buffers and CPU resources.